LPC1850 Datasheet, PDF (44/84 Pages) NXP Semiconductors – 32-bit ARM Cortex-M3 MCU; up to 200 kB SRAM; Ethernet, two High-speed USB, LCD

NXP Semiconductors
LPC1850/30/20/10
32-bit ARM Cortex-M3 microcontroller
7.13.4.1 Features
• I²C0 is a standard I²C compliant bus interface with open-drain pins. I²C0 also
supports Fast mode plus with bit rates up to 1 Mbit/s.
• I²C1 uses standard I/O pins with bit rates of up to 400 kbit/s (Fast I²C-bus).
• Easy to configure as master, slave, or master/slave.
• Programmable clocks allow versatile rate control.
• Bidirectional data transfer between masters and slaves.
• Multi-master bus (no central master).
• Arbitration between simultaneously transmitting masters without corruption of serial
data on the bus.
• Serial clock synchronization allows devices with different bit rates to communicate via
one serial bus.
• Serial clock synchronization can be used as a handshake mechanism to suspend and
resume serial transfer.
• The I²C-bus can be used for test and diagnostic purposes.
• All I²C-bus controllers support multiple address recognition and a bus monitor mode.
7.13.5 I²S interface
The I²S-bus provides a standard communication interface for digital audio applications.
The I²S-bus specification defines a 3-wire serial bus using one data line, one clock line,
and one word select signal. The basic I²S-bus connection has one master, which is
always the master, and one slave. The I²S-bus interface provides a separate transmit and
receive channel, each of which can operate as either a master or a slave.
7.13.5.1 Features
• The interface has separate input/output channels each of which can operate in master
or slave mode.
• Capable of handling 8-bit, 16-bit, and 32-bit word sizes.
• Mono and stereo audio data supported.
• The sampling frequency can range from 16 kHz to 96 kHz (16, 22.05, 32, 44.1, 48,
96) kHz.
• Support for an audio master clock.
• Configurable word select period in master mode (separately for I²S-bus input and
output).
• Two 8-word FIFO data buffers are provided, one for transmit and one for receive.
• Generates interrupt requests when buffer levels cross a programmable boundary.
• Two DMA requests, controlled by programmable buffer levels. These are connected
to the GPDMA block.
• Controls include reset, stop and mute options separately for I²S-bus input and I²S-bus
output.
LPC1850_30_20_10
Objective data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 3 January 2011
© NXP B.V. 2011. All rights reserved.
44 of 84