ISP1583 Datasheet, PDF (61/100 Pages) NXP Semiconductors – Hi-Speed Universal Serial Bus peripheral controller

NXP Semiconductors
ISP1583
Hi-Speed USB peripheral controller
Each interrupt bit can individually be cleared by writing logic 1. The DMA Interrupt bit can
be cleared by writing logic 1 to the related interrupt source bit in the DMA Interrupt
Reason register, followed by writing logic 1 to the DMA bit of the Interrupt register.
Table 82. Interrupt register: bit allocation
Bit
31
30
29
28
Symbol
reserved
Reset
-
-
-
-
Bus reset
-
-
-
-
Access
-
-
-
-
Bit
23
22
21
20
Symbol
EP6TX
EP6RX
EP5TX
EP5RX
Reset
0
0
0
0
Bus reset
0
0
0
0
Access
R/W
R/W
R/W
R/W
Bit
15
14
13
12
Symbol
EP2TX
EP2RX
EP1TX
EP1RX
Reset
0
0
0
0
Bus reset
0
0
0
0
Access
R/W
R/W
R/W
R/W
Bit
7
6
5
4
Symbol
VBUS
DMA
HS_STAT RESUME
Reset
0
0
0
0
Bus reset
0
0
0
0
Access
R/W
R/W
R/W
R/W
27
-
-
-
19
EP4TX
0
0
R/W
11
EP0TX
0
0
R/W
3
SUSP
0
0
R/W
26
-
-
-
18
EP4RX
0
0
R/W
10
EP0RX
0
0
R/W
2
PSOF
0
0
R/W
25
EP7TX
0
0
R/W
17
EP3TX
0
0
R/W
9
reserved
-
-
-
1
SOF
0
0
R/W
24
EP7RX
0
0
R/W
16
EP3RX
0
0
R/W
8
EP0SETUP
0
0
R/W
0
BRESET
0
1
R/W
ISP1583_7
Product data sheet
Table 83.
Bit
31 to 26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
Interrupt register: bit description
Symbol
Description
-
reserved
EP7TX
logic 1 indicates the endpoint 7 TX buffer as interrupt source
EP7RX
logic 1 indicates the endpoint 7 RX buffer as interrupt source
EP6TX
logic 1 indicates the endpoint 6 TX buffer as interrupt source
EP6RX
logic 1 indicates the endpoint 6 RX buffer as interrupt source
EP5TX
logic 1 indicates the endpoint 5 TX buffer as interrupt source
EP5RX
logic 1 indicates the endpoint 5 RX buffer as interrupt source
EP4TX
logic 1 indicates the endpoint 4 TX buffer as interrupt source
EP4RX
logic 1 indicates the endpoint 4 RX buffer as interrupt source
EP3TX
logic 1 indicates the endpoint 3 TX buffer as interrupt source
EP3RX
logic 1 indicates the endpoint 3 RX buffer as interrupt source
EP2TX
logic 1 indicates the endpoint 2 TX buffer as interrupt source
EP2RX
logic 1 indicates the endpoint 2 RX buffer as interrupt source
EP1TX
logic 1 indicates the endpoint 1 TX buffer as interrupt source
EP1RX
logic 1 indicates the endpoint 1 RX buffer as interrupt source
EP0TX
logic 1 indicates the endpoint 0 data TX buffer as interrupt source
Rev. 07 — 22 September 2008
© NXP B.V. 2008. All rights reserved.
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