ISP1583 Datasheet, PDF (36/100 Pages) NXP Semiconductors – Hi-Speed Universal Serial Bus peripheral controller

NXP Semiconductors
ISP1583
Hi-Speed USB peripheral controller
ISP1583_7
Product data sheet
Table 31. OTG register: bit description
Bit Symbol Description^[1]
7 to 6 -
reserved
5
DP
Data Pulsing: Used for data-line pulsing to toggle DP to generate the required
data-line pulsing signal. The default value of this bit is logic 0. This bit must be
cleared when data-line pulsing is completed.
4
BSESS B-Session Valid: The device can initiate another V_BUS discharge sequence
VALID after data-line pulsing and V_BUS pulsing, and before it clears this bit and detects
a session valid.
This bit is latched to logic 1 once V_BUS exceeds the B-device session valid
threshold. Once set, it remains at logic 1. To clear this bit, write logic 1. (The
ISP1583 continuously updates this bit to logic 1 when the B-session is valid. If
the B-session is valid after it is cleared, it is set back to logic 1 by the ISP1583).
0 — It implies that SRP has failed. To proceed to a normal operation, the device
can restart SRP, clear bit OTG or proceed to an error handling process.
1 — It implies that the B-session is valid. The device clears bit OTG, goes into
normal operation mode, and sets bit SOFTCT (DP pull-up) in the Mode register.
The OTG host has a maximum of 5 s before it responds to a session request.
During this period, the ISP1583 may request to suspend. Therefore, the device
firmware must wait for some time if it wishes to know the SRP result (success: if
there is minimum response from the host within 5 s; failure: if there is no
response from the host within 5 s).
3
INIT
Initial Condition: Write logic 1 to clear this bit. Wait for more than 2 ms and
COND check the bit status. If it reads logic 0, it means that V_BUS remains lower than
0.8 V, and DP or DM are at SE0 during the elapsed time. The device can then
start a B-device SRP. If it reads logic 1, it means that the initial condition of SRP
is violated. So, the device must abort SRP.
The bit is set to logic 1 by the ISP1583 when initial conditions are not met, and
only writing logic 1 clears the bit. (If initial conditions are not met after this bit
has been cleared, it will be set again).
Remark: This implementation does not cover the case if an initial SRP condition
is violated when this bit is read and data-line pulsing is started.
2
DISCV Discharge V_BUS: Set to logic 1 to discharge V_BUS. The device discharges V_BUS
before starting a new SRP. The discharge can take as long as 30 ms for V_BUS to
be charged less than 0.8 V. This bit must be cleared (write logic 0) before a
session end.
1
VP
V_BUS Pulsing: Used for V_BUS pulsing to toggle VP to generate the required
V_BUS pulsing signal. This bit must be set for more than 16 ms and must be
cleared before 26 ms.
0
OTG On-The-Go:
1 — Enables the OTG function. The V_BUS sensing functionality will be disabled.
0 — Normal operation. All OTG control bits will be masked. Status bits are
undefined.
[1] No interrupt is designed for OTG. The V_BUS interrupt, however, may assert as a side effect during the V_BUS
pulsing.
When OTG is in progress, the V_BUS interrupt may be set because V_BUS is charged over the V_BUS sensing
threshold or the OTG host has turned on the V_BUS supply to the device. Even if the V_BUS interrupt is found
during SRP, the device must complete data-line pulsing and V_BUS pulsing before starting the
B_SESSION_VALID detection.
OTG implementation applies to the device with self-power capability. If the device works in sharing mode, it
must provide a switch circuit to supply power to the ISP1583 core during SRP.
Rev. 07 — 22 September 2008
© NXP B.V. 2008. All rights reserved.
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