ISP1507C_ISP1507D Datasheet, PDF (61/74 Pages) NXP Semiconductors – ULPI Hi-Speed Universal Serial Bus host and peripheral transceiver

NXP Semiconductors
ISP1507C; ISP1507D
ULPI HS USB host and peripheral transceiver
V_OH
t_HSR, t_FR, t_LR
90 %
t_HSF, t_FF, t_LF
90 %
10 %
V_OL
Fig 21. Rise time and fall time
10 %
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1.8 V
logic input 0.9 V
0V
V_OH
differential
data lines
V_OL
t_PLH(drv)
V_CRS
0.9 V
t_PHL(drv)
V_CRS
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Fig 22. Timing of TX_DAT and TX_SE0 to DP and DM
1.8 V
logic _{0.9 V}
input
0V
V_OH
differential
data lines
V_OL
t_PZH
t_PZL
V_CRS
0.9 V
t_PHZ
t_PLZ
V_OH − 0.3 V
V_OL + 0.3 V
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2.0 V
differential
data lines
0.8 V
V_OH
V_CRS
t_PLH(rcv)
t_PLH(se)
logic output
0.9 V
V_OL
V_CRS
t_PHL(rcv)
t_PHL(se)
0.9 V
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Fig 23. Timing of TX_ENABLE to DP and DM
Fig 24. Timing of DP and DM to RX_RCV, RX_DP and
RX_DM
15.1 ULPI timing
ULPI timing requirements are given in Figure 25. This timing applies to synchronous
mode only. All timing is measured with respect to the ISP1507 CLOCK pin. All signals are
clocked on the rising edge of CLOCK.
CLOCK
CONTROL IN
(STP)
DATA IN
(8-BIT)
t_su(STP) t_h(STP)
t_su(DATA) t_h(DATA)
CONTROL OUT
(DIR, NXT)
DATA OUT
(8-BIT)
Fig 25. ULPI timing
t_d(DIR),
t_d(NXT)
t_d(DATA)
t_d(DIR),
t_d(NXT)
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ISP1507C_ISP1507D_1
Product data sheet
Rev. 01 — 28 May 2008
© NXP B.V. 2008. All rights reserved.
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