ISP1507C_ISP1507D Datasheet, PDF (1/74 Pages) NXP Semiconductors – ULPI Hi-Speed Universal Serial Bus host and peripheral transceiver

ISP1507C; ISP1507D
ULPI Hi-Speed Universal Serial Bus host and peripheral
transceiver
Rev. 01 — 28 May 2008
Product data sheet
1. General description
The ISP1507 is a Universal Serial Bus (USB) high-speed host and peripheral transceiver
that is fully compliant with Universal Serial Bus Specification Rev. 2.0 and UTMI+ Low Pin
Interface (ULPI) Specification Rev. 1.1.
The ISP1507 can transmit and receive USB data at high-speed (480 Mbit/s), full-speed
(12 Mbit/s) and low-speed (1.5 Mbit/s), and provides a pin-optimized, physical layer
front-end attachment to USB host, peripheral and OTG devices.
It is ideal for use in portable electronic devices, such as mobile phones, digital still
cameras, digital video cameras, Personal Digital Assistants (PDAs) and digital audio
players. It allows USB Application-Specific Integrated Circuits (ASICs), Programmable
Logic Devices (PLDs) and any system chip set to interface with the physical layer of the
USB through a 12-pin interface.
The ISP1507 can interface to the link with digital I/O voltages in the range of 1.65 V to
3.6 V.
The ISP1507 is available in HVQFN24 package.
2. Features
I Fully complies with:
N Universal Serial Bus Specification Rev. 2.0
N UTMI+ Low Pin Interface (ULPI) Specification Rev. 1.1
I Interfaces to host and peripheral cores; optimized for stand-alone and embedded host
applications with an external V_BUS supply; stand-alone peripheral cores, and Session
Request Protocol (SRP)-capable peripheral cores
I Complete Hi-Speed USB physical front-end solution that supports high-speed
(480 Mbit/s), full-speed (12 Mbit/s) and low-speed (1.5 Mbit/s)
N Integrated 45 Ω ± 10 % high-speed termination resistors, 1.5 kΩ ± 5 % full-speed
device pull-up resistor, and 15 kΩ ± 5 % host termination resistors
N Integrated parallel-to-serial and serial-to-parallel converters to transmit and receive
N USB clock and data recovery to receive USB data up to ±500 ppm
N Insertion of stuff bits during transmit and discarding of stuff bits during receive
N Non-Return-to-Zero Inverted (NRZI) encoding and decoding
N Supports bus reset, suspend, resume and high-speed detection handshake (chirp)
I Supports SRP for reduced power consumption
N Complete control over bus resistors
N Data line and V_BUS pulsing session request methods