PSMN2R5-30YL_09 Datasheet, PDF (6/14 Pages) NXP Semiconductors – N-channel TrenchMOS logic level FET

NXP Semiconductors
PSMN2R5-30YL
N-channel TrenchMOS logic level FET
Table 6. Characteristics …continued
Symbol Parameter
Conditions
Min Typ Max Unit
Source-drain diode
V_SD
source-drain voltage I_S = 25 A; V_GS = 0 V; T_j = 25 °C; see Figure 17 -
0.79 1.2 V
t_rr
reverse recovery time I_S = 20 A; dI_S/dt = -100 A/µs; V_GS = 0 V;
Q_r
recovered charge
V_DS = 20 V
-
39
-
ns
-
38
-
nC
[1] Tested to JEDEC standards where applicable.
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80
I_D
(A)
60
40
T_j = 150 °C
25 °C
20
0
0
1
2
3 _{VGS (V)} 4
I_D ¹⁶⁰ ₁₀
(A)
140 _4.5
120
100
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V_GS (V) = 3.2
3
80
2.8
60
40
2.6
20
2.4
2.2
0
0
2
4
6
8
10
V_DS (V)
Fig 5. Transfer characteristics: drain current as a
Fig 6. Output characteristics: drain current as a
function of gate-source voltage; typical values
function of drain-source voltage; typical values
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003aac658
140
9
g_fs
R_DSon
(S)
(mΩ)
120
7
V_GS (V) = 3.2
100
5
80
60
40
0
20
40
60 _{ID (A)} 80
3
4.5
10
1
0
50
100 _{ID (A)} 150
Fig 7. Forward transconductance as a function of
drain current; typical values
Fig 8. Drain-source on-state resistance as a function
of drain current; typical values
PSMN2R5-30YL_3
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 03 — 28 December 2009
© NXP B.V. 2009. All rights reserved.
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