PSMN2R5-30YL_09 Datasheet, PDF (3/14 Pages) NXP Semiconductors – N-channel TrenchMOS logic level FET

NXP Semiconductors
PSMN2R5-30YL
N-channel TrenchMOS logic level FET
120
I_D
(A)
(1)
100
80
60
40
20
0
0
50
003aac656
100
150
200
T_mb (°C)
120
P_der
(%)
80
03aa16
40
0
0
50
100
150
200
T_mb (°C)
Fig 1. Continuous drain current as a function of
mounting base temperature
10³
I_D
(A)
10²
Limit R_DSon = V_DS / I_D
10
1
10^-1
10^-1
1
Fig 2. Normalized total power dissipation as a
function of mounting base temperature
003aac659
10 μs
100 μs
1 ms
DC
10 ms
100 ms
10
V_DS (V)
10²
Fig 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage
PSMN2R5-30YL_3
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 03 — 28 December 2009
© NXP B.V. 2009. All rights reserved.
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