74HC5555D-T Datasheet, PDF (6/23 Pages) NXP Semiconductors – Programmable delay timer with oscillator

Philips Semiconductors
Programmable delay timer with oscillator
Product specification
74HC/HCT5555
TEST MODE
Set S₃ to a logic LOW level, this will divide the 24 stage counter into three, parallel clocking, 8-stage counters. Set S₀,
S₁ and S₂ to a logic HIGH level, this programs the counter to divide-by 2⁸ (256). Apply a trigger pulse and clock in 255
pulses, this sets all flip-flop stages to a logic HIGH level. Set S₃ to a logic HIGH level, this causes the counter to divide-by
2²⁴. Clock one more pulse into the RS input, this causes a logic 0 to ripple through the counter and output Q/Q goes from
HIGH-to-LOW level. This method of testing the delay counter is faster than clocking in 2²⁴ (16 777 216) clock pulses.
FUNCTION TABLE
MR
H
L
L
INPUTS
A
X
↑
X
Notes
1. H = HIGH voltage level
L = LOW voltage level
X = don't care
↑ = LOW-to-HIGH transition
↓ = HIGH-to-LOW transition.
OUTPUTS
B
Q
Q
X
L
H
X
one HIGH level
one LOW level
output pulse
output pulse
↓
one HIGH level
one LOW level
output pulse
output pulse
September 1993
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