74HC5555D-T Datasheet, PDF (21/23 Pages) NXP Semiconductors – Programmable delay timer with oscillator

Philips Semiconductors
Programmable delay timer with oscillator
Product specification
74HC/HCT5555
Timing Component Limitations
The oscillator frequency is mainly
determined by R_tC_t, provided R2 ≈
2R_t and R2C2 << R_tC_t. The function
of R2 is to minimize the influence of
the forward voltage across the input
protection diodes on the frequency.
The stray capacitance C2 should be
kept as small as possible. In
consideration of accuracy, C_t must be
larger than the inherent stray
capacitance. R_t must be larger than
the “ON” resistance in series with it,
which typically is 280 Ω at
V_CC = 2 V, 130 Ω at V_CC = 4.5 V and
100 Ω at V_CC = 6 V. The
recommended values for these
components to maintain agreement
with the typical oscillation formula are:
C_t > 50 pF, up to any practical value,
10 kΩ < R_t < 1 MΩ.
In order to avoid start-up problems,
R_t >> 1 kΩ.
Typical Crystal Oscillator
In Fig.15, R2 is the power limiting
resistor. For starting and maintaining
oscillation a minimum
transconductance is necessary, so
R2 should not be too large. A practical
value for R2 is 2.2 kΩ. Above 14 MHz
it is recommended replacement of R2
by a capacitor with a typical value of
35 pF.
Accuracy
Device accuracy is very precise for
long time delays and has an accuracy
of better than 1% for short time delays
(1% applies to values ≥ 400 ns).
Tolerances are dependent on the
external components used, either RC
network or crystal oscillator.
Start-up Using External Clock
The start of the timing pulse is
initiated directly by the trigger pulse
(asynchronously with respect to the
oscillator clock). Triggering on a clock
HIGH or clock LOW results in the
following:
• clock = HIGH; the timing pulse may
be lengthened by a maximum of
t_W/2 (t_W = clock pulse width)
• clock = LOW; the timing pulse may
be shortened by a maximum of t_W/2
(t_W = clock pulse width).
This effect can be minimized by
selecting more delay stages. When
using only one or two delay stages, it
is recommended to use an external
time base that is synchronized with
the negative-edge of the clock.
Start-up Using RC Oscillator
The first clock cycle is ≈35% of a time
period too long. This effect can also
be minimized by selecting more delay
stages.
Start-up Using Crystal Oscillator
A crystal oscillator requires at least
two clock cycles to start-up plus an
unspecified period (ms) before the
amplitude of the clock signal
increases to its expected level.
Although this device also operates at
lower clock amplitudes, it is
recommended to select the
continuously running mode
(OSC CON = HIGH) to prevent
start-up delays.
Termination of the Timing Pulse
The end of the timing pulse is
synchronized with the falling edge of
the oscillator clock. The timing pulse
may lose synchronization under the
following conditions:
• high clock frequency and large
number of stages are selected.
This depends on the dynamic
relationship that exists between the
clock frequency and the ripple
through delay of the subsequent
stages.
Synchronization
When frequencies higher than those
specified in the Table
'Synchronization limits' are used, the
termination of timing pulse will lose
synchronization with the falling edge
of the oscillator. The unsynchronized
timing pulse introduces errors, which
can be minimized by increasing the
number of stages used e.g. a 20 MHz
clock frequency using all 24 stages
will result in a frequency division of
16 777 225 instead of 16 777 216, an
error of 0.0005%.
The amount of error increases at high
clock frequencies as the number of
stages decrease. A clock frequency
of 40 MHz and 4 stages selected
results in a division of 18 instead of
16, a 12.5% error. Application
example:
• If a 400 ns timing pulse was
required it would be more accurate
to utilize a 5 MHz clock frequency
using 1 stage or a 10 MHz clock
frequency using 2 stages (due to
synchronization with falling edge of
the oscillator) than a 40 MHz clock
frequency and 4 stages
(synchronization is lost).
September 1993
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