UJA1069 Datasheet, PDF(55/64 Page) NXP Semiconductors

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UJA1069 Datasheet, PDF (55/64 Pages) NXP Semiconductors – LIN fail-safe system basis chip

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NXP Semiconductors

UJA1069

LIN fail-safe system basis chip

Table 26. Dynamic characteristics â¦continued

Tvj = â40 Â°C to +150 Â°C; VBAT42 = 5.5 V to 52 V; VBAT14 = 5.5 V to 27 V; VBAT42 â¥ VBAT14 â 1 V; unless otherwise speciï¬ed. All

voltages are deï¬ned with respect to ground. Positive currents ï¬ow into the IC.[1]

Symbol

Parameter

Conditions

Min

Typ Max

Unit

tTXDL(dom)(dis) TXDL permanent dominant Active mode; VTXDL = 0 V

disable time

Battery monitoring

tBAT42(L)

BAT42 LOW time for

setting PWONS

Âµs

tSENSE(L)

BAT42 LOW time for

setting BATFI

Âµs

Power supply V1; pin V1

tV1(CLT)

V1 clamped LOW time

during ramp-up of V1

Start-up mode; V1 active

229

283

Power supply V3; pin V3

tw(CS)

cyclic sense period

V3C[1:0] = 10; see Figure 13

V3C[1:0] = 11; see Figure 13

ton(CS)

cyclic sense on-time

V3C[1:0] = 10; see Figure 13

345

423

Âµs

V3C[1:0] = 11; see Figure 13

345

423

Âµs

Wake-up input; pin WAKE

tWU(ipf)

tsu(CS)

input port ï¬lter time

cyclic sense sample setup

time

VBAT42 = 5 V to 27 V

VBAT42 = 27 V to 52 V

V3C[1:0] = 11 or 10;

see Figure 13

120

Âµs

250

Âµs

310

390

Âµs

Watchdog

tWD(ETP)

earliest watchdog trigger

point

programmed Nominal

Watchdog Period (NWP);

Normal mode

0.45 Ã NWP -

0.55 Ã NWP

tWD(LTP)

latest watchdog trigger

point

programmed nominal

watchdog period; Normal

mode, Standby mode and

Sleep mode

0.9 Ã NWP -

1.1 Ã NWP

tWD(init)

watchdog initializing period watchdog time-out in Start-up

229

283

mode

Fail-safe mode

tret

retention time

Fail-safe mode; wake-up

detected

1.3

1.5 1.7

Reset output; pin RSTN

tRSTN(CHT)

clamped HIGH time,

RSTN driven LOW internally

115

141

pin RSTN

but RSTN pin remains HIGH

tRSTN(CLT)

clamped LOW time,

RSTN driven HIGH internally

229

283

pin RSTN

but RSTN pin remains LOW

tRSTN(INT)

interrupt monitoring time INTN = LOW

229

283

tRSTNL

reset lengthening time

after internal or external reset

0.9

1.1

has been released; RLC = 0

after internal or external reset

has been released; RLC =1

UJA1069_3

Product data sheet

Rev. 03 â 10 September 2007

55 of 64

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