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UJA1069 Datasheet, PDF (11/64 Pages) NXP Semiconductors – LIN fail-safe system basis chip | |||
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NXP Semiconductors
UJA1069
LIN fail-safe system basis chip
When an interrupt event occurs the application software has to read the Interrupt register
within tRSTN(INT). Otherwise a fail-safe system reset is forced and Start-up mode will be
entered. If the application has read out the Interrupt register within the speciï¬ed time, it
can decide whether to switch into Normal mode via an SPI access or to stay in Standby
mode.
The following operations are possible from Standby mode:
⢠Cyclic wake-up by the watchdog via an interrupt signal to the microcontroller (the
microcontroller is triggered periodically and checked for the correct response)
⢠Cyclic wake-up by the watchdog via a reset signal (a reset is performed periodically;
the SBC provides information about the reset source to allow different start
sequences after reset)
⢠Wake-up by activity on the LIN-bus via an interrupt signal to the microcontroller
⢠Wake-up by bus activity on the LIN-bus via a reset signal
⢠Wake-up by increasing the microcontroller supply current without a reset signal
(where a stable supply is needed for the microcontroller RAM contents to remain valid
and wake-up from an external application not connected to the SBC)
⢠Wake-up by increasing the microcontroller supply current with a reset signal
⢠Wake-up due to a falling edge at pin WAKE forcing an interrupt to the microcontroller
⢠Wake-up due to a falling edge at pin WAKE forcing a reset signal
6.2.6 Sleep mode
In Sleep mode the microcontroller power supply (V1) and the INH/LIMP controlled
external supplies are switched off entirely, resulting in minimum system power
consumption. In this mode, the watchdog runs in Time-out mode or is completely off.
Entering Sleep mode results in an immediate LOW level on pin RSTN, thus stopping any
operation of the microcontroller. The INH/LIMP output is ï¬oating in parallel and pin V1 is
disabled. It is also possible for V3 to be ON, OFF or in Cyclic mode to supply external
wake-up switches.
If the watchdog is not disabled in software, it will continue to run and force a system reset
upon overï¬ow of the programmed period time. The SBC enters Start-up mode and pin V1
becomes active again. This behavior can be used for a cyclic wake-up from Sleep mode.
Depending on the application, the following operations can be selected from Sleep mode:
⢠Cyclic wake-up by the watchdog (only in Time-out mode); a reset is performed
periodically, the SBC provides information about the reset source to allow different
start sequences after reset
⢠Wake-up by activity on the LIN-bus or falling edge at pin WAKE
⢠An overload on V3, only if V3 is in a cyclic or in continuously ON mode
6.2.7 Flash mode
Flash mode can only be entered from Normal mode by entering a speciï¬c Flash mode
entry sequence. This fail-safe control sequence comprises three consecutive write
accesses to the Mode register, within the legal windows of the watchdog, using the
UJA1069_3
Product data sheet
Rev. 03 â 10 September 2007
© NXP B.V. 2007. All rights reserved.
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