SSTUB32865 Datasheet, PDF (5/28 Pages) NXP Semiconductors – 1.8 V 28-bit 1 : 2 registered buffer with parity for DDR2-800 RDIMM applications

NXP Semiconductors
SSTUB32865
1.8 V DDR2-800 registered buffer with parity
1
2
A VREF
SELDR
B
D1
D2
C
D3
D4
D
D6
D5
E
D7
D8
F
D11
D9
G
D18
D12
H CSGATEEN D15
J
CK
DCS0
K
CK
DCS1
L RESET
D14
M
D0
D10
N
D17
D16
P
D19
D21
R
D13
D20
T DODT1 DODT0
U DCKE0 DCKE1
V
VREF
MCL
3
4
PARIN
n.c.
n.c.
n.c.
VDDL
VDDL
VDDL
VDDL
DCS2
GND
DCS3
GND
GND
VDDL
GND
GND
MCL
MCL
PTYERR
n.c.
5
n.c.
n.c.
GND
GND
GND
GND
GND
GND
VDDL
GND
GND
VDDL
VDDL
VDDL
MCH
MCH
6
7
QCKE1A QCKE0A
QCKE1B QCKE0B
n.c.
VDDL
n.c.
VDDR
VDDL
VDDL
VDDR
GND
Q3B
Q3A
Q12B
Q12A
8
Q21A
Q21B
GND
GND
VDDR
VDDR
GND
VDDR
GND
VDDR
GND
VDDR
VDDR
GND
Q7B
Q7A
160-ball, 12 × 18 grid; top view.
An empty cell indicates no ball is populated at that grid point.
n.c. denotes a no-connect (ball present but not connected to the die).
MCL denotes a pin that must be connected LOW.
MCH denotes a pin that must be connected HIGH.
Fig 3. Ball mapping
9
Q19A
Q19B
GND
GND
VDDR
VDDR
GND
VDDR
GND
VDDR
GND
VDDR
GND
GND
Q4B
Q4A
10
Q18A
Q18B
Q13B
Q13A
11
12
Q17B
Q17A
QODT0B QODT0A
QODT1B QODT1A
Q20B
Q20A
Q16B
Q16A
Q1B
Q1A
Q2B
Q2A
Q5B
Q5A
QCS0B QCS0A
QCS1B QCS1A
Q6B
Q6A
Q10B
Q10A
Q9B
Q9A
Q11B
Q11A
Q15B
Q15A
Q14B
Q14A
Q0B
Q8B
Q0A
Q8A
002aac017
SSTUB32865_3
Product data sheet
Rev. 03 — 27 March 2007
© NXP B.V. 2007. All rights reserved.
5 of 28