SSTUB32865 Datasheet, PDF (1/28 Pages) NXP Semiconductors – 1.8 V 28-bit 1 : 2 registered buffer with parity for DDR2-800 RDIMM applications

SSTUB32865
1.8 V 28-bit 1 : 2 registered buffer with parity for DDR2-800
RDIMM applications
Rev. 03 — 27 March 2007
Product data sheet
1. General description
The SSTUB32865 is a 1.8 V 28-bit 1 : 2 register specifically designed for use on two rank
by four (2R × 4) and similar high-density Double Data Rate 2 (DDR2) memory modules. It
is similar in function to the JEDEC-standard 14-bit DDR2 register, but integrates the
functionality of the normally required two registers in a single package, thereby freeing up
board real-estate and facilitating routing to accommodate high-density Dual In-line
Memory Module (DIMM) designs.
The SSTUB32865 also integrates a parity function, which accepts a parity bit from the
memory controller, compares it with the data received on the D-inputs and indicates
whether a parity error has occurred on its open-drain PTYERR pin (active LOW).
It further offers added features over the JEDEC standard register in that it can be
configured for normal or high output drive strength, simply by tying input pin SELDR either
HIGH of LOW as needed. This allows use in different module designs varying from low to
high density designs by picking the appropriate drive strength to match net loading
conditions. Furthermore, the SSTUB32865 features two additional chip select inputs,
which allow more versatile enabling and disabling in densely populated memory modules.
Both added features (drive strength and chip selects) are fully backward compatible to the
JEDEC standard register.
The SSTUB32865 is packaged in a 160-ball, 12 × 18 grid, 0.65 mm ball pitch, thin profile
fine-pitch ball grid array (TFBGA) package, which, while requiring a minimum
9 mm × 13 mm of board space, allows for adequate signal routing and escape using
conventional card technology.
2. Features
I 28-bit data register supporting DDR2
I Fully compliant to JEDEC standard for SSTUB32865
I Supports 2 rank by 4 DIMM density by integrating equivalent functionality of two
JEDEC-standard DDR2 registers (that is, 2 × SSTUB32864 or 2 × SSTUB32866)
I Parity checking function across 22 input data bits
I Parity out signal
I Controlled multi-impedance output impedance drivers enable optimal signal integrity
and speed
I Meets or exceeds SSTUB32865 JEDEC standard speed performance
I Supports up to 450 MHz clock frequency of operation
I Programmable for normal or high output drive
I Optimized pinout for high-density DDR2 module design