GTL2107 Datasheet, PDF (5/19 Pages) NXP Semiconductors – 12-bit GTL−/GTL/GTL+ to LVTTL translator

NXP Semiconductors
GTL2107
12-bit GTL−/GTL/GTL+ to LVTTL translator
Table 7. CPU SMI_L control
H = HIGH voltage level; L = LOW voltage level.
Inputs
Output
10AI1/10AI2
9BI
10BO1/10BO2
L
L
L
L
H
L
H
L
L
H
H
H
Table 8. PROCHOT L control
H = HIGH voltage level; L = LOW voltage level.
Inputs
Input/output
EN2
5BI/6BI
5A/6A (open-drain)
H
L
L
H
H
L^[2]
H
H
H
L
H
L^[2]
L
H
H
L
L
H
L
L
L^[2]
Output
7BO1/7BO2
H^[1]
L
H
L
H
H
H
[1] The enable on 7BO1/7BO2 includes a delay that prevents the transient condition (where 5BI/6BI goes from
LOW to HIGH, and the LOW to HIGH on 5A/6A lags up to 100 ns) from causing a low glitch on the
7BO1/7BO2 outputs.
[2] Open-drain input/output terminal is driven to logic LOW state by an external driver.
Table 9. Southbridge NMI control
H = HIGH voltage level; L = LOW voltage level.
Input
Input/output
11BI
11A (open-drain)
L
H
L
L^[1]
H
L
Output
11BO
L
H
H
[1] Open-drain input/output terminal is driven to logic LOW state by an external driver.
GTL2107_5
Product data sheet
Rev. 05 — 23 December 2009
© NXP B.V. 2009. All rights reserved.
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