GTL2107 Datasheet, PDF (2/19 Pages) NXP Semiconductors – 12-bit GTL−/GTL/GTL+ to LVTTL translator

NXP Semiconductors
GTL2107
12-bit GTL−/GTL/GTL+ to LVTTL translator
4. Ordering information
Table 2. Ordering information
T_amb = −40 °C to +85 °C.
Type
number
Topside Package
mark
Name
GTL2107PW GTL2107 TSSOP28
Description
plastic thin shrink small outline package; 28 leads; body width 4.4 mm
Version
SOT361-1
5. Functional diagram
GTL VREF
1AO
LVTTL outputs
(open-drain)
2AO
5A
LVTTL inputs/outputs
(open-drain)
6A
LVTTL input EN1
GTL2107
1
2
3
4
5
6
GTL input 11BI
7
27
1BI
GTL inputs
26
2BI
&
25
7BO1
GTL outputs
&
24
7BO2
23
EN2 LVTTL input
1
22
11BO GTL output
LVTTL input/output
(open-drain)
11A
8
GTL input 9BI
9
3AO
10
LVTTL outputs
(open-drain)
4AO
11
DELAY⁽¹⁾
DELAY⁽¹⁾
21
5BI
20
6BI
GTL inputs
19
3BI
18
4BI
10AI1
12
LVTTL inputs
10AI2
13
1
17
10BO1
1
GTL outputs
16
10BO2
15
9AO LVTTL output
002aac745
(1) The enable on 7BO1/7BO2 include a delay that prevents the transient condition (where 5BI/6BI go from LOW to HIGH, and the
LOW to HIGH on 5A/6A lags up to 100 ns) from causing a LOW glitch on the 7BO1/7BO2 outputs.
Fig 1. Logic diagram of GTL2107
GTL2107_5
Product data sheet
Rev. 05 — 23 December 2009
© NXP B.V. 2009. All rights reserved.
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