SC16C554BIB80-T Datasheet, PDF (44/58 Pages) NXP Semiconductors – 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte FIFOs

NXP Semiconductors
SC16C554B/554DB
5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte FIFOs
start
bit
data bits (0 to 7)
next
data
parity stop start
bit bit bit
RX
D0 D1 D2 D3 D4 D5 D6 D7
RXRDY
IOR
Fig 25. Receive ready timing in non-FIFO mode
t_25d
active data
ready
t_26d
active
002aab063
start
bit
data bits (0 to 7)
parity stop
bit bit
RX
D0 D1 D2 D3 D4 D5 D6 D7
first byte that
reaches the
trigger level
RXRDY
IOR
Fig 26. Receive ready timing in FIFO mode
t_25d
active data
ready
t_26d
active
002aab064
SC16C554B_554DB
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 8 June 2010
© NXP B.V. 2010. All rights reserved.
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