SC16C554BIB80-T Datasheet, PDF (25/58 Pages) NXP Semiconductors – 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte FIFOs

NXP Semiconductors
SC16C554B/554DB
5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte FIFOs
SC16C554B/554DB
D0 to D7
R/W
RESET
DATA BUS
AND
CONTROL
LOGIC
TRANSMIT
FIFO
REGISTERS
FLOW
CONTROL
LOGIC
TRANSMIT
SHIFT
REGISTER
TXA to TXD
RECEIVE
FIFO
REGISTERS
RECEIVE
SHIFT
REGISTER
RXA to RXD
A0 to A4
CS
REGISTER
SELECT
LOGIC
16/68
IRQ
TXRDY
RXRDY
INTERRUPT
CONTROL
LOGIC
FLOW
CONTROL
LOGIC
CLOCK AND
BAUD RATE
GENERATOR
XTAL1 XTAL2
Fig 16. Internal Loopback mode diagram (68 mode)
MODEM
CONTROL
LOGIC
RTSA to RTSD
CTSA to CTSD
DTRA to DTRD
DSRA to DSRD
OP1A to OP1D
RIA to RID
OP2A to OP2D
CDA to CDD
002aaa884
SC16C554B_554DB
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 8 June 2010
© NXP B.V. 2010. All rights reserved.
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