P89V51RB2_09 Datasheet, PDF (43/80 Pages) NXP Semiconductors – 8-bit 80C51 5 V low power 16/32/64 kB flash microcontroller with 1 kB RAM

NXP Semiconductors
P89V51RB2/RC2/RD2
8-bit microcontrollers with 80C51 core
clock output and input for the master and slave modes, respectively. The SPI clock
generator will start following a write to the master devices SPI data register. The written
data is then shifted out of the MOSI pin on the master device into the MOSI pin of the
slave device. Following a complete transmission of one byte of data, the SPI clock
generator is stopped and the SPIF flag is set. An SPI interrupt request will be generated if
the SPI Interrupt Enable bit (SPIE) and the Serial Port Interrupt Enable bit (ES) are both
set.
An external master drives the Slave Select input pin, SS/P1[4], low to select the SPI
module as a slave. If SS/P1[4] has not been driven low, then the slave SPI unit is not
active and the MOSI/P1[5] port can also be used as an input port pin.
CPHA and CPOL control the phase and polarity of the SPI clock. Figure 18 and Figure 19
show the four possible combinations of these two bits.
MSB master LSB
8-BIT SHIFT REGISTER
MISO
MOSI
MISO
MOSI
MSB slave LSB
8-BIT SHIFT REGISTER
SPI
CLOCK GENERATOR
Fig 17. SPI master-slave interconnection
SPICLK
SS
V_DD
SPICLK
SS
V_SS
002aaa528
Table 28. SPCR - SPI control register (address D5H) bit allocation
Bit addressable; Reset source(s): any reset; Reset value: 0000 0000B
Bit
7
6
5
4
3
2
Symbol SPIE
SPE DORD MSTR CPOL CPHA
1
SPR1
0
SPR0
Table 29.
Bit
7
6
5
4
3
SPCR - SPI control register (address D5H) bit description
Symbol
Description
SPIE
If both SPIE and ES are set to one, SPI interrupts are enabled.
SPE
SPI enable bit. When set enables SPI.
DORD
Data transmission order. 0 = MSB first; 1 = LSB first in data
transmission.
MSTR
Master/slave select. 1 = master mode, 0 = slave mode.
CPOL
Clock polarity. 1 = SPICLK is high when idle (active LOW),
0 = SPICLK is low when idle (active HIGH).
P89V51RB2_RC2_RD2_5
Product data sheet
Rev. 05 — 12 November 2009
© NXP B.V. 2009. All rights reserved.
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