SAA7160ETV2 Datasheet, PDF (42/57 Pages) NXP Semiconductors – PCI Express based audio and video bridge

NXP Semiconductors
SAA7160
PCI Express based audio and video bridge
Any device addressed by a master is considered a slave. Generation of clock signals on
the I²C-bus is always the responsibility of the master device; each master generates its
own clock signals when transferring data on the bus. Bus clock signals from a master can
only be altered when they are stretched by a slow-slave device holding down the clock line
or by another master when arbitration occurs.
SDA_A
global I²C-bus
SCL_A
I²C-BUS
INTERFACE 2
CLOCK GENERATOR
IN
OUT
I²C-BUS
CORE 1
data I²C-bus control
IRQ
I²C-bus configuration
CLOCK GENERATOR
SDA_B
global I²C-bus
SCL_B
I²C-BUS
INTERFACE 1
IN
OUT
I²C-BUS
CORE 0
data I²C-bus control
IRQ
I²C-bus configuration
BOOT EEPROM
Fig 10. I²C-bus structure overview
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6.5 I²S-bus input interface
The SAA7160 has two independent audio slave interface circuits for serial input of digital
audio data streams. The audio interface circuits are based on the I²S-bus standard but
can be configured to several data and timing formats (with respect to framing, bit clock
and synchronization).
List of key features:
• Supports I²S-bus, LSB and MSB justified formats
• Sample size up to 32 bit
• Standard stereo I²S-bus (MSB first, 1-bit delay from word select, left and right data in
a frame)
• LSB first with 1-bit to 32-bits data per channel
• Raw sample mode where the serial data for each active serial channel is sampled at
each sampling clock edge along with the word-select signal
Each of the slave I²S-bus interfaces consists two data lines, a word select line and a serial
clock line. The word select line distinguishes between the left and the right channel
information of the data lines. It is possible to sample up to 32 bits per channel, and there
are 4 channels on each module available.
The following block diagram shows the structure of the different I²S-bus interfaces.
SAA7160_1
Product data sheet
Rev. 01 — 25 February 2008
© NXP B.V. 2008. All rights reserved.
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