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| LPC2104 Datasheet, PDF (4/41 Pages) NXP Semiconductors – Single-chip 32-bit microcontrollers; 128 kB ISP/IAP Flash with 64 kB/32 kB/16 kB RAM | |||
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NXP Semiconductors
4. Block diagram
LPC2104/2105/2106
Single-chip 32-bit microcontrollers
TMS(2) TDI(2) RTCK
TRST(2) TCK(2) TDO(2)
XTAL2
XTAL1 RESET
LPC2104/2105/2106
HIGH-SPEED
P0
GPIO(3)
32 PINS TOTAL
ARM7 LOCAL BUS
TEST/DEBUG
INTERFACE
ARM7TDMI-S
AHB BRIDGE
PLL
system
clock
SYSTEM
FUNCTIONS
VECTORED
INTERRUPT
CONTROLLER
AMBA Advanced High-performance
Bus (AHB)
VDD(3V3)
VDD(1V8)
VSS
EINT[2:0](1)
CAP0[2:0](1)
CAP1[3:0](1)
MAT0[2:0](1)
MAT1[3:0](1)
P0[31:0]
INTERNAL
SRAM
CONTROLLER
INTERNAL
FLASH
CONTROLLER
16/32/64 kB
SRAM
128 kB
FLASH
EXTERNAL
INTERRUPTS
CAPTURE/
COMPARE
TIMER 0/TIMER 1
GENERAL
PURPOSE I/O
AHB
DECODER
AHB TO APB APB
BRIDGE DIVIDER
Advanced Peripheral
Bus (APB)
I2C-BUS SERIAL
INTERFACE
SPI/SSP(3)
SERIAL INTERFACE
UART0/UART1
PWM[6:1](1)
PWM0
REAL-TIME CLOCK
WATCHDOG
TIMER
SYSTEM
CONTROL
SCL(1)
SDA(1)
SCK(1)
MOSI(1)
MISO(1)
SSEL(1)
TXD[1:0](1)
RXD[1:0](1)
DSR1(1), CTS1(1),
RTS1(1), DTR1(1),
DCD1(1), RI1(1)
002aaa412
(1) Shared with GPIO.
(2) When test/debug interface is used, GPIO/other functions sharing these pins are not available.
(3) Available on LPC2104/2105/2106/01 only.
Fig 1. Block diagram
LPC2104_2105_2106_7
Product data sheet
Rev. 07 â 20 June 2008
© NXP B.V. 2008. All rights reserved.
4 of 41
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