LPC2104 Datasheet, PDF (1/41 Pages) NXP Semiconductors – Single-chip 32-bit microcontrollers; 128 kB ISP/IAP Flash with 64 kB/32 kB/16 kB RAM

LPC2104/2105/2106
Single-chip 32-bit microcontrollers; 128 kB ISP/IAP flash with
16/32/64 kB RAM
Rev. 07 — 20 June 2008
Product data sheet
1. General description
The UART are based on a 16/32-bit ARM7TDMI-S CPU with real-time emulation and
embedded trace support, together with 128 kB of embedded high speed flash memory. A
128-bit wide memory interface and a unique accelerator architecture enable 32-bit code
execution at maximum clock rate. For critical code size applications, the alternative 16-bit
Thumb mode reduces code by more than 30 % with minimal performance penalty.
Due to their tiny size and low power consumption, these microcontrollers are ideal for
applications where miniaturization is a key requirement, such as access control and
point-of-sale. With a wide range of serial communications interfaces and on-chip SRAM
options up to 64 kB, they are very well suited for communication gateways and protocol
converters, soft modems, voice recognition and low end imaging, providing both large
buffer size and high processing power. Various 32-bit timers, PWM channels, and 32
GPIO lines make these microcontrollers particularly suitable for industrial control and
medical systems.
Remark: Throughout the data sheet, the term LPC2104/2105/2106 will apply to devices
with and without /00 and /01 suffixes. Suffixes will be used to differentiate devices
whenever they include new features.
2. Features
2.1 New features implemented in LPC2104/2105/2106/01 devices
I Fast GPIO port enables port pin toggling up to 3.5 times faster than the original device
and also allows for a port pin to be read at any time regardless of its function.
I UART 0/1 include fractional baud rate generator, autobauding capabilities, and
handshake flow-control fully implemented in hardware.
I Buffered SSP serial controller supporting SPI, 4-wire SSI, and Microwire formats.
I SPI programmable data length and master mode enhancement.
I Diversified Code Read Protection (CRP) enables different security levels to be
implemented.
I General purpose timers can operate as external event counters.
2.2 Key common features
I 16/32-bit ARM7TDMI-S processor.
I 16/32/64 kB on-chip static RAM.
I 128 kB on-chip flash program memory. 128-bit-wide interface/accelerator enables high
speed 60 MHz operation.