74F543 Datasheet, PDF (4/15 Pages) NXP Semiconductors – Octal registered transceiver, non-inverting 3-State

NXP Semiconductors
74F543
Octal latched transceiver with dual enable; 3-state
6. Functional description
6.1 Function table
Table 3.
Input
OEXX
H
X
L
Function selection^[1]
EXX
X
H
↑
L
L
L
L
L
L
LEXX
X
X
L
↑
L
H
An or Bn
X
X
h
l
h
l
H
L
X
Output
Bn or An
Z
Z
Z
Z
H
L
H
L
NC
Status
disabled
disabled + latch
latch + display
transparent
hold
[1] H = HIGH voltage level;
h = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock transition of LEXX or EXX (XX = AB or BA);
L = LOW voltage level;
l = LOW voltage level one set-up time prior to the LOW-to-HIGH clock transition of LEXX or EXX (XX = AB or BA);
↑ = LOW-to-HIGH clock transition of LEXX or EXX (XX = AB or BA);
NC = no change;
X = don’t care;
Z = high-impedance OFF-state.
6.2 Description
The 74F543 contains two sets of eight D-type latches, with separate control pins for each
set.
Using data flow from A-to-B as an example, when the A-to-B enable (EAB) input, the
A-to-B latch enable (LEAB) input and the A-to-B output latch enable (OEAB) are all LOW,
the A-to-B path is transparent.
A subsequent LOW-to-HIGH transition of the LEAB signal puts the A data into the latches
where it is stored and the B outputs no longer change with the A inputs. With EAB and
OEAB both LOW, the 3-state B output buffers are active and display the data present at
the outputs of the A latches.
Control of data flow from B-to-A is similar, but using the EBA, LEBA, and OEBA inputs.
74F543_4
Product data sheet
Rev. 04 — 26 January 2010
© NXP B.V. 2010. All rights reserved.
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