SC68C752B Datasheet, PDF (39/48 Pages) NXP Semiconductors – 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs and Motorola uP interface

NXP Semiconductors
SC68C752B
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs
RXA, RXB
Start
bit
data bits (0 to 7)
parity Stop
bit bit
D0 D1 D2 D3 D4 D5 D6 D7
first byte that
reaches the
trigger level
RXRDYA,
RXRDYB
CS (read)
Fig 20. Receive ready timing in FIFO mode
t_d15
active data
ready
t_d16
active
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TXA, TXB
IRQ
CS (write)
Start
bit
data bits (0 to 7)
parity
bit
Stop
bit
next
data
Start
bit
D0 D1 D2 D3 D4 D5 D6 D7
5 data bits
6 data bits
7 data bits
t_d12
t_d13
active
active
transmitter ready
t_d14
active
Fig 21. Transmit timing
16 baud rate clock
002aab093
SC68C752B_4
Product data sheet
Rev. 04 — 20 January 2010
© NXP B.V. 2010. All rights reserved.
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