SC68C752B Datasheet, PDF (12/48 Pages) NXP Semiconductors – 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs and Motorola uP interface

NXP Semiconductors
SC68C752B
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs
6.4 Reset
Table 5 summarizes the state of register after reset.
Table 5. Register reset functions
Register
Reset control
Interrupt Enable Register
RESET
Interrupt Identification Register RESET
FIFO Control Register
RESET
Line Control Register
RESET
Modem Control Register
RESET
Line Status Register
RESET
Modem Status Register
RESET
Enhanced Feature Register
RESET
Receiver Holding Register
RESET
Transmitter Holding Register RESET
Transmission Control Register RESET
Trigger Level Register
RESET
Reset state
all bits cleared
bit 0 is set; all other bits cleared
all bits cleared
reset to 0001 1101 (1Dh)
all bits cleared
bits 5 and 6 set; all other bits cleared
bits 0 to 3 cleared; bits 4 to 7 input signals
all bits cleared
pointer logic cleared
pointer logic cleared
all bits cleared
all bits cleared
Remark: Registers DLL, DLM, SPR, XON1, XON2, XOFF1, XOFF2 are not reset by the
top-level reset signal RESET, that is, they hold their initialization values during reset.
Table 6 summarizes the state of registers after reset.
Table 6. Signal RESET functions
Signal
Reset control
TXn
RESET
RTSn
RESET
DTRn
RESET
RXRDYn
RESET
TXRDYn
RESET
Reset state
HIGH
HIGH
HIGH
HIGH
LOW
SC68C752B_4
Product data sheet
Rev. 04 — 20 January 2010
© NXP B.V. 2010. All rights reserved.
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