LPC11C12 Datasheet, PDF (38/49 Pages) NXP Semiconductors – 32-bit ARM Cortex-M0 microcontroller; 16/32 kB flash, 8 kB SRAM; C_CAN

LPC11C12/C14 NXP Semiconductors
Table 14.
Symbol
t_DH
t_v(Q)
t_h(Q)
Dynamic characteristics of SPI pins in SPI mode
Parameter
Conditions
data hold time
in SPI mode
[3][4]
data output valid time in SPI mode
[3][4]
data output hold time in SPI mode
[3][4]
Min
3 × T_cy(PCLK) + 4
-
-
[1] T_cy(clk) = (SSPCLKDIV × (1 + SCR) × CPSDVSR) / f_main. The clock cycle time derived from
th^--T-e^yS^pDP^RI^Ab^Fi^Tt^32M-r^Da^××aRte^xADTTT^FRcc_c^TyyA_y⁽⁽₍^PPDF_c^CC_l^TR_k)^LLADKKis^FR))Ta^DA++DFRf¹⁵u^TRA1n^AFDc^TFRti^To^ADn^DFRTRDAo^ARf^FDUnnnTt^FARh^sssTnFADe^{TiDFRtTRDAARDFTFDARTRFADTADFRTFRDATADRF}
main clock frequency f_main, the SPI peripheral clock divider (SSPCLKDIV), the SPI SCR parameter (specified in the SSP0CR0 register),
and the SPI CPSDVSR parameter (specified in the SPI clock prescale register).
[2] T_amb = −40 °C to 85 °C.
[3] T_cy(clk) = 12 × T_cy(PCLK).
[4] T_amb = 25 °C; for normal voltage supply range: V_DD = 3.3 V.
SCK (CPOL = 0)
SCK (CPOL = 1)
MOSI
MISO
T_cy(clk)
t_clk(H)
t_clk(L)
t_v(Q)
DATA VALID
DATA VALID
DATA VALID
t_DS
t_DH
DATA VALID
t_h(Q)
CPHA = 1
MOSI
MISO
t_v(Q)
DATA VALID
DATA VALID
DATA VALID
t_DS
t_DH
DATA VALID
t_h(Q)
CPHA = 0
002aae829
Pin names SCK, MISO, and MOSI refer to pins for both SPI peripherals, SPI0 and SPI1.
Fig 20. SPI master timing in SPI mode
LPC11C12_C14_0
Preliminary data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 00.05 — 6 May 2010
© NXP B.V. 2010. All rights reserved.
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