UJA1069_09 Datasheet, PDF (34/64 Pages) NXP Semiconductors – LIN fail-safe system basis chip

NXP Semiconductors
UJA1069
LIN fail-safe system basis chip
Table 11.
Bit
12
11 to 5
4
3
2
1
0
Physical Layer Control and Physical Layer Control Feedback register bit description …continued
Symbol
Description
Value Function
RO
Read Only
1
read the register selected by RRS without writing to the
Physical Layer Control register
0
read the register selected by RRS and write to Physical
Layer Control register
-
reserved
000 0000 reserved for SBCs with CAN transceiver
LMC
LIN Mode Control
1
LIN Active mode (in Normal mode and Flash mode only)
0
LIN Active mode disabled
LSC
LIN Slope Control
1
up to 10.4 kbit/s (low slope)
0
up to 20 kbit/s (normal)
LDC
LIN Driver Control
1
increased LIN driver current capability
0
LIN driver in conformance with the LIN 2.0 standard
-
reserved
0
reserved for SBCs with CAN transceiver
LTC
LIN Transmitter
Control^[1]
1
LIN transmitter is disabled
0
LIN transmitter is enabled
[1] In case of an RXDL / TXDL interfacing failure the LIN transmitter is disabled without setting LTC. Recovery from such a failure is
automatic when LIN communication (with correct interfacing levels) is received. Manual recovery is also possible by setting and clearing
the LTC bit under software control.
6.12.10 Special Mode register and Special Mode Feedback register
These registers allow configuration of global SBC parameters during start-up of a system
and allow the settings to be read back.
Table 12. Special Mode register and Special Mode Feedback register bit description
Bit
Symbol
Description
Value Function
15 and 14 A1, A0
register address
01
select Special Mode register
13
RRS
Read Register Select 0
read the Interrupt Enable Feedback register
1
read the Special Mode Feedback register
12
RO
Read Only
1
read the register selected by RRS without writing to the
Special Mode register
0
read the register selected by RRS and write to the
Special Mode register
11 and 10 -
reserved
0
reserved for future use; should remain cleared to ensure
compatibility with future functions which might use this bit
9
ISDM
Initialize Software
1
initialization of software development mode
Development Mode^[1] ₀
normal watchdog interrupt, reset monitoring and fail-safe
behavior
8
-
reserved
0
reserved for SBCs with CAN transceiver
7
-
reserved
0
reserved for future use; should remain cleared to ensure
compatibility with future functions which might use this bit
6 and 5 WDPRE[1:0] Watchdog Prescaler 00
watchdog prescale factor 1
01
watchdog prescale factor 1.5
10
watchdog prescale factor 2.5
11
watchdog prescale factor 3.5
UJA1069_4
Product data sheet
Rev. 04 — 28 October 2009
© NXP B.V. 2009. All rights reserved.
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