UJA1069_09 Datasheet, PDF (28/64 Pages) NXP Semiconductors – LIN fail-safe system basis chip

NXP Semiconductors
UJA1069
LIN fail-safe system basis chip
Table 5.
Bit
11 to 6
Mode register bit description (bits 11 to 6)^[1] …continued
Symbol
Description
Value
Time
Normal
mode (ms)
NWP[5:0] Nominal
00 1001
14
Watchdog Period _{00 1100}
28
WDPRE = 11 (as _{01 0010}
56
set in the Special
Mode register) ^{01 0100}
112
01 1011
140
10 0100
168
10 1101
196
11 0011
224
11 0101
252
11 0110
280
Standby
mode (ms)
70
140
280
560
1120
2240
3584
7168
14336
OFF^[2]
Flash mode
(ms)
70
140
280
560
1120
2240
3584
7168
14336
28672
Sleep mode
(ms)
560
1120
2240
3584
7168
10752
14336
21504
28672
OFF^[3]
[1] The nominal watchdog periods are directly related to the SBC internal oscillator. The given values are valid for f_osc = 512 kHz.
[2] See Section 6.4.4.
[3] The watchdog is immediately disabled on entering Sleep mode, with watchdog OFF behavior selected, because pin RSTN is
immediately pulled LOW by the mode change. V1 is switched off after pulling pin RSTN LOW to guarantee a safe Sleep mode entry
without dips on V1. See Section 6.4.4.
6.12.4 System Status register
This register allows status information to be read back from the SBC. This register can be
read in all modes.
Table 6. System Status register bit description
Bit
Symbol
Description
Value
15 and 14 A1, A0
register address
00
13
RRS
Read Register Select 0
12
RO
Read Only
1
0
Function
read System Status register
read System Status register without writing to Mode
register
read System Status register and write to Mode register
UJA1069_4
Product data sheet
Rev. 04 — 28 October 2009
© NXP B.V. 2009. All rights reserved.
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