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SC16C752B_10 Datasheet, PDF (34/47 Pages) NXP Semiconductors – 5 V, 2.2 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs
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NXP Semiconductors
SC16C752B
5 V, 2.2 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs
[5] Except XTAL2, VOL = 1 V typical.
[6] These junction temperatures reflect simulated conditions. Absolute maximum junction temperature is 150 °C. The customer is
responsible for verifying junction temperature.
[7] Measurement condition, normal operation other than Sleep mode:
VCC = 3.3 V; Tamb = 25 °C. Full duplex serial activity on all two serial (UART) channels at the clock frequency specified in the
recommended operating conditions with divisor of 1.
[8] Sleep mode current might be higher if there is activity on the UART data bus during Sleep mode.
11. Dynamic characteristics
Table 26. Dynamic characteristics
Tamb = −40 °C to +85 °C; VCC = 2.5 V, 3.3 V ± 10 % or 5 V ± 10 %, unless specified otherwise.
Symbol Parameter
Conditions
VCC = 2.5 V
Min
Max
td1
IOR delay from chip select
10
-
td2
read cycle delay
25 pF load
20
-
td3
delay from IOR to data
25 pF load
-
77
td4
data disable time
25 pF load
-
15
td5
IOW delay from chip select
td6
write cycle delay
10
-
25
-
td7
delay from IOW to output
25 pF load
-
100
td8
delay to set interrupt from modem input 25 pF load
-
100
td9
delay to reset interrupt from IOR
td10
delay from stop to set interrupt
25 pF load
-
100
-
1TRCLK[1]
td11
delay from IOR to reset interrupt
td12
delay from start to set interrupt
td13
delay from IOW to transmit start
25 pF load
-
100
-
100
8
24TRCLK[1]
td14
delay from IOW to reset interrupt
td15
delay from stop to set RXRDYn
-
100
-
1TRCLK[1]
td16
delay from IOR to reset RXRDYn
-
100
td17
delay from IOW to set TXRDYn
td18
delay from start to reset TXRDYn
-
100
-
16TRCLK[1]
td19
delay between successive assertion of
IOW and IOR
-
20
th1
chip select hold time from IOR
0
-
th2
chip select hold time from IOW
0
-
th3
data hold time
15
-
th4
address hold time
0
-
th5
hold time from XTAL1 clock HIGH-to-LOW
transition to IOW or IOR release
20
-
tp1
clock cycle period
10
-
tp2
fXTAL1
tw(RESET)
clock cycle period
frequency on pin XTAL1
pulse width on pin RESET
10
-
[2]
-
48
[3] 100
-
tsu1
address set-up time
0
-
VCC = 3.3 V or 5 V Unit
Min
Max
0
-
ns
20
-
ns
-
26
ns
-
15
ns
10
-
ns
25
-
ns
-
33
ns
-
24
ns
-
24
ns
-
1TRCLK[1] s
-
29
ns
-
100 ns
8
24TRCLK[1] s
-
70
ns
-
1TRCLK[1] s
-
75
ns
-
70
ns
-
16TRCLK[1] s
-
20
ns
0
-
ns
0
-
ns
15
-
ns
0
-
ns
20
-
ns
6
-
ns
6
-
ns
-
80
MHz
40
-
ns
0
-
ns
SC16C752B
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 6 — 30 November 2010
© NXP B.V. 2010. All rights reserved.
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