SC16C752B_10 Datasheet, PDF (13/47 Pages) NXP Semiconductors – 5 V, 2.2 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs

NXP Semiconductors
SC16C752B
5 V, 2.2 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs
6.5 Interrupts
The SC16C752B has interrupt generation and prioritization (six prioritized levels of
interrupts) capability. The Interrupt Enable Register (IER) enables each of the six types of
interrupts and the INTA/INTB signal in response to an interrupt generation. The IER can
also disable the interrupt system by clearing bit 0 to bit 3 and bit 5 to bit 7. When an
interrupt is generated, the IIR indicates that an interrupt is pending and provides the type
of interrupt through IIR[5:0]. Table 6 summarizes the interrupt control functions.
Table 6.
IIR[5:0]
00 0001
00 0110
00 1100
00 0100
00 0010
00 0000
01 0000
10 0000
Interrupt control functions
Priority
level
Interrupt type
None
none
1
receiver line status
2
RX time-out
2
RHR interrupt
3
THR interrupt
4
modem status
5
Xoff interrupt
6
CTS, RTS
Interrupt source
Interrupt reset method
none
OE, FE, PE, or BI errors occur in
characters in the RX FIFO
stale data in RX FIFO
DRDY (data ready)
(FIFO disable)
RX FIFO above trigger level
(FIFO enable)
TFE (THR empty)
(FIFO disable)
TX FIFO passes above trigger level
(FIFO enable)
MSR[3:0] = logic 0
receive Xoff character(s)/special
character
RTSn pin or CTSn pin change state
from active (LOW) to inactive (HIGH)
none
FE, PE, BI: all erroneous
characters are read from the
RX FIFO.
OE: read LSR
read RHR
read RHR
read IIR or a write to the THR
read MSR
receive Xon character(s)/Read of
IIR
read IIR
It is important to note that for the framing error, parity error, and break conditions, LSR[7]
generates the interrupt. LSR[7] is set when there is an error anywhere in the RX FIFO,
and is cleared only when there are no more errors remaining in the FIFO. LSR[4:2] always
represent the error status for the received character at the top of the RX FIFO. Reading
the RX FIFO updates LSR[4:2] to the appropriate status for the new character at the top of
the FIFO. If the RX FIFO is empty, then LSR[4:2] are all zeros.
For the Xoff interrupt, if an Xoff flow character detection caused the interrupt, the interrupt
is cleared by an Xon flow character detection. If a special character detection caused the
interrupt, the interrupt is cleared by a read of the LSR.
SC16C752B
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 6 — 30 November 2010
© NXP B.V. 2010. All rights reserved.
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