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| PCF8533 Datasheet, PDF (32/45 Pages) NXP Semiconductors – Universal LCD driver for low multiplex rates | |||
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NXP Semiconductors
PCF8533
Universal LCD driver for low multiplex rates
VLCD
VDD
R
â¤
tr
2Cb
HOST
MICRO-
PROCESSOR/
MICRO-
CONTROLLER
SDAACK
SDA
VDD VLCD
SCL
80 segment drives
SYNC
CLK
PCF8533
OSC
A0 A1 A2 SA0 VSS
BP0 to BP3
(open-circuit)
LCD PANEL
(up to 5120
elements)
SDAACK
VDD VLCD
SDA
SCL
SYNC
CLK
OSC
PCF8533
80 segment drives
4 backplanes
BP0 to BP3
mgl754
VSS
A0 A1 A2 SA0 VSS
Fig 22. Cascaded PCF8533 configuration
The SYNC line is provided to maintain the correct synchronization between all cascaded
PCF8533s. This synchronization is guaranteed after the power-on reset. The only time
that SYNC is likely to be needed is if synchronization is accidentally lost (e.g. by noise in
adverse electrical environments, or by the definition of a multiplex mode when PCF8533s
with different SA0 levels are cascaded).
SYNC is organized as an input/output pin; the output selection being realized as an
open-drain driver with an internal pull-up resistor. A PCF8533 asserts the SYNC line at the
onset of its last active backplane signal and monitors the SYNC line at all other times.
Should synchronization in the cascade be lost, it will be restored by the first PCF8533 to
assert SYNC. The timing relationships between the backplane waveforms and the SYNC
signal for the various drive modes of the PCF8533 are shown in Figure 23.
PCF8533_4
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 04 â 5 March 2010
© NXP B.V. 2010. All rights reserved.
32 of 45
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