PCAL9538A Datasheet, PDF (30/43 Pages) NXP Semiconductors – Low-voltage 8-bit I2C-bus and SMBus low power I/O port with interrupt, reset and Agile I/O

NXP Semiconductors
PCAL9538A
Low-voltage 8-bit I²C-bus/SMBus low power I/O port
V_DD
a. Interrupt load configuration
DUT
RL = 4.7 kΩ
INT
CL = 100 pF
002aah069
START condition
slave address
acknowledge
from slave
R/W
8 bits (one data byte)
from port
SDA S 1 1 1 0 0 A1 A0 1 A
DATA 1
acknowledge
from slave
no acknowledge
from master
data from port
STOP
condition
A
DATA 2
1P
INT
data into
port
SCL 1 2 3 4 5 6 7 8 9
t_rst(INT)
t_v(INT)
A
A
ADDRESS
t_su(D)
DATA 1
B
t_{rst(INT) B}
DATA 2
INT
0.5 × V_DD
t_v(INT)
SCL R/W
A
t_rst(INT)
0.7 × V_DD
0.3 × V_DD
Pn
0.5 × V_DD
INT
0.5 × V_DD
View A - A
View B - B
002aah116
b. Voltage waveforms
C_L includes probe and jig capacitance.
All inputs are supplied by generators having the following characteristics: PRR  10 MHz; Z_o = 50 ; t_r/t_f  30 ns.
All parameters and waveforms are not applicable to all devices.
Fig 30. Interrupt load circuit and voltage waveforms
PCAL9538A
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 10 December 2012
© NXP B.V. 2012. All rights reserved.
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