PCAL9538A Datasheet, PDF (12/43 Pages) NXP Semiconductors – Low-voltage 8-bit I2C-bus and SMBus low power I/O port with interrupt, reset and Agile I/O

NXP Semiconductors
PCAL9538A
Low-voltage 8-bit I²C-bus/SMBus low power I/O port
7. Bus transactions
The PCAL9538A is an I²C-bus slave device. Data is exchanged between the master and
PCAL9538A through write and read commands using I²C-bus. The two communication
lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be
connected to a positive supply via a pull-up resistor when connected to the output stages
of a device. Data transfer may be initiated only when the bus is not busy.
7.1 Write commands
Data is transmitted to the PCAL9538A by sending the device address and setting the
Least Significant Bit (LSB) to a logic 0 (see Figure 4 for device address). The command
byte is sent after the address and determines which register receives the data that follows
the command byte. There is no limitation on the number of data bytes sent in one write
transmission.
SCL 1 2 3 4 5 6 7 8 9
slave address
command byte
SDA S 1 1 1 0 0 A1 A0 0 A 0 0 0 0 0 0 0 1 A
data to port
DATA 1
STOP
condition
AP
START condition
write to port
data out from port
R/W acknowledge
from slave
Fig 7. Write to Output port register
acknowledge
from slave
acknowledge
from slave
t_v(Q)
DATA 1 VALID
002aah102
SCL 1 2 3 4 5 6 7 8 9
slave address
command byte
SDA S 1 1 1 0 0 A1 A0 0 A 0 1/0 1/0 0 1/0 1/0 1/0 1/0 A
data to register
DATA 1
START condition
R/W acknowledge
from slave
acknowledge
from slave
Fig 8. Write to Configuration or Polarity inversion registers
STOP
condition
AP
acknowledge
from slave
002aah103
PCAL9538A
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 10 December 2012
© NXP B.V. 2012. All rights reserved.
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