PSMN4R0-30YL_09 Datasheet, PDF (3/14 Pages) NXP Semiconductors – N-channel TrenchMOS logic level FET

NXP Semiconductors
PSMN4R0-30YL
N-channel TrenchMOS logic level FET
4. Limiting values
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter
Conditions
V_DS
V_DGR
V_GS
I_D
drain-source voltage
drain-gate voltage
gate-source voltage
drain current
I_DM
peak drain current
P_tot
total power dissipation
T_stg
storage temperature
T_j
junction temperature
Source-drain diode
T_j ≥ 25 °C; T_j ≤ 175 °C
T_j ≥ 25 °C; T_j ≤ 175 °C; R_GS = 20 kΩ
V_GS = 10 V; T_mb = 100 °C; see Figure 1
V_GS = 10 V; T_mb = 25 °C; see Figure 1
t_p ≤ 10 µs; pulsed; T_mb = 25 °C; see Figure 3
T_mb = 25 °C; see Figure 2
I_S
source current
I_SM
peak source current
Avalanche ruggedness
T_mb = 25 °C
t_p ≤ 10 µs; pulsed; T_mb = 25 °C
E_DS(AL)S
non-repetitive
V_GS = 10 V; T_j(init) = 25 °C; I_D = 99 A; V_sup ≤ 30 V;
drain-source avalanche R_GS = 50 Ω; unclamped
energy
Min Max Unit
-
30
V
-
30
V
-20 20
V
-
76
A
-
100 A
-
396 A
-
69
W
-55 175 °C
-55 175 °C
-
99
A
-
396 A
-
41
mJ
120
I_D
(A)
(1)
100
80
60
40
20
0
0
50
003aac649
100
150
200
T_mb (°C)
120
P_der
(%)
80
03aa16
40
0
0
50
100
150
200
T_mb (°C)
Fig 1. Continuous drain current as a function of
mounting base temperature
Fig 2. Normalized total power dissipation as a
function of mounting base temperature
PSMN4R0-30YL_3
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 03 — 31 December 2009
© NXP B.V. 2009. All rights reserved.
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