GTL2018 Datasheet, PDF (3/14 Pages) NXP Semiconductors – 8-bit LVTTL to GTL transceiver

NXP Semiconductors
6. Pinning information
6.1 Pinning
GTL2018
8-bit LVTTL to GTL transceiver
GND 1
B0 2
B1 3
B2 4
B3 5
VREF 6
GND 7
B4 8
B5 9
B6 10
B7 11
GND 12
GTL2018PW
24 V_CC
23 A0
22 A1
21 A2
20 A3
19 GND
18 A4
17 A5
16 A6
15 A7
14 V_CC
13 DIR
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Fig 2. Pin configuration for TSSOP24
6.2 Pin description
Table 3.
Symbol
GND
B0
B1
B2
B3
B4
B5
B6
B7
VREF
DIR
V_CC
A7
A6
A5
A4
A3
A2
A1
A0
Pin description
Pin
1, 7, 12, 19
2
3
4
5
8
9
10
11
6
13
14, 24
15
16
17
18
20
21
22
23
Description
ground (0 V)
data inputs/outputs (B side, GTL)
GTL reference voltage
direction control input (LVTTL)
positive supply voltage
data inputs/outputs (A side, LVTTL)
GTL2018_1
Product data sheet
Rev. 01 — 15 February 2007
© NXP B.V. 2007. All rights reserved.
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