GTL2018 Datasheet, PDF (1/14 Pages) NXP Semiconductors – 8-bit LVTTL to GTL transceiver

GTL2018
8-bit LVTTL to GTL transceiver
Rev. 01 — 15 February 2007
Product data sheet
1. General description
The GTL2018 is an octal translating transceiver designed for 3.3 V LVTTL system
interface with a GTL−/GTL/GTL+ bus.
The direction pin (DIR) allows the part to function as either a GTL-to-LVTTL sampling
receiver or as an LVTTL-to-GTL interface.
The GTL2018 LVTTL inputs (only) are tolerant up to 5.5 V, allowing direct access to TTL
or 5 V CMOS inputs.
2. Features
I Operates as an octal GTL−/GTL/GTL+ sampling receiver or as an LVTTL to
GTL−/GTL/GTL+ driver
I 3.0 V to 3.6 V operation with 5 V tolerant LVTTL input
I GTL input and output 3.6 V tolerant
I V_ref adjustable from 0.5 V to 0.5V_CC
I Partial power-down permitted
I Latch-up protection exceeds 500 mA per JESD78
I ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per
JESD22-A115, and 1000 V CDM per JESD22-CC101
I Package offered: TSSOP24
3. Quick reference data
Table 1.
Symbol
C_i
Quick reference data
Parameter
input capacitance
C_io
input/output capacitance
GTL; V_ref = 0.8 V; V_TT = 1.2 V
t_PLH
LOW-to-HIGH propagation delay
t_PHL
HIGH-to-LOW propagation delay
t_PLH
LOW-to-HIGH propagation delay
t_PHL
HIGH-to-LOW propagation delay
Conditions
control inputs;
V_I = 3.0 V or 0 V
A port; V_O = 3.0 V or 0 V
B port; V_O = V_TT or 0 V
An to Bn; see Figure 3
An to Bn; see Figure 3
Bn to An; see Figure 4
Bn to An; see Figure 4
Min Typ
-
2
-
4.6
-
3.4
Max Unit
2.5 pF
6
pF
4.3 pF
-
2.8
5
ns
-
3.4
7
ns
-
5.2
8
ns
-
4.9
7
ns