GTL2012 Datasheet, PDF (3/14 Pages) NXP Semiconductors – 2-bit LVTTL to GTL transceiver

NXP Semiconductors
6. Pinning information
6.1 Pinning
GTL2012
2-bit LVTTL to GTL transceiver
A0 1
A1 2
DIR 3
GND 4
GTL2012DP
8 V_CC
7 VREF
6 B0
5 B1
002aab606
Fig 2. Pin configuration for TSSOP8
(MSOP8)
A0 1
A1 2
DIR 3
GND 4
GTL2012DC
8 V_CC
7 VREF
6 B0
5 B1
002aac398
Fig 3. Pin configuration for VSSOP8
6.2 Pin description
Table 3.
Symbol
A0
A1
DIR
GND
B1
B0
VREF
V_CC
Pin description
Pin
1
2
3
4
5
6
7
8
Description
data inputs/outputs (A side, LVTTL)
direction control input (LVTTL)
ground (0 V)
data inputs/outputs (B side, GTL)
GTL reference voltage
positive supply voltage
7. Functional description
Refer to Figure 1 “Logic diagram of GTL2012”.
7.1 Function table
Table 4. Function table
H = HIGH voltage level; L = LOW voltage level.
Input
Input/output
DIR
A (LVTTL)
H
inputs
L
An = Bn
B (GTL)
Bn = An
inputs
GTL2012_1
Product data sheet
Rev. 01 — 9 August 2007
© NXP B.V. 2007. All rights reserved.
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