GTL2012 Datasheet, PDF (1/14 Pages) NXP Semiconductors – 2-bit LVTTL to GTL transceiver

GTL2012
2-bit LVTTL to GTL transceiver
Rev. 01 — 9 August 2007
Product data sheet
1. General description
The GTL2012 is a 2-bit translating transceiver designed for 3.3 V system interface with a
GTL−/GTL/GTL+ bus.
The direction pin (DIR) allows the part to function as either a GTL-to-LVTTL sampling
receiver or as an LVTTL-to-GTL interface.
The GTL2012 LVTTL inputs (only) are tolerant up to 5.5 V allowing direct access to TTL or
5 V CMOS inputs.
2. Features
I Operates as a 2-bit GTL−/GTL/GTL+ sampling receiver or as an LVTTL to
GTL−/GTL/GTL+ driver
I 3.0 V to 3.6 V operation with 5 V tolerant LVTTL input
I GTL input and output 3.6 V tolerant
I V_ref adjustable from 0.5 V to 0.5V_CC
I Partial power-down permitted
I Latch-up protection exceeds 500 mA per JESD78
I ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per
JESD22-A115, and 1000 V CDM per JESD22-CC101
I Package offered: TSSOP8 (MSOP8) and VSSOP8
3. Quick reference data
Table 1. Quick reference data
Recommended operating conditions; T_amb = 25 °C
Symbol Parameter
Conditions
C_i
input capacitance
control inputs; V_I = 3.0 V or 0 V
C_io
input/output capacitance
A port; V_O = 3.0 V or 0 V
GTL; V_ref = 0.8 V; V_TT = 1.2 V
B port; V_O = V_TT or 0 V
t_PLH
LOW-to-HIGH propagation delay
An to Bn; see Figure 4
t_PHL
HIGH-to-LOW propagation delay
An to Bn; see Figure 4
t_PLH
LOW-to-HIGH propagation delay
Bn to An; see Figure 5
t_PHL
HIGH-to-LOW propagation delay
Bn to An; see Figure 5
[1] All typical values are measured at V_CC = 3.3 V and T_amb = 25 °C.
Min Typ^[1] Max Unit
-
2
2.5 pF
-
4.6 6
pF
-
3.4 4.3 pF
-
2.8 5
ns
-
3.4 7
ns
-
5.2 8
ns
-
4.9 7
ns