74HC240-Q100 Datasheet, PDF (3/16 Pages) NXP Semiconductors – Octal buffer/line driver; 3-state; inverting

NXP Semiconductors
74HC240-Q100; 74HCT240-Q100
Octal buffer/line driver; 3-state; inverting
5. Pinning information
5.1 Pinning
74HC240-Q100
74HCT240-Q100
1OE 1
1A0 2
2Y0 3
1A1 4
2Y1 5
1A2 6
2Y2 7
1A3 8
2Y3 9
GND 10
20 V_CC
19 2OE
18 1Y0
17 2A0
16 1Y1
15 2A1
14 1Y2
13 2A2
12 1Y3
11 2A3
aaa-003157
Fig 4. Pin configuration SO20, TSSOP20
terminal 1
index area
74HC240-Q100
74HCT240-Q100
1A0 2
2Y0 3
1A1 4
2Y1 5
1A2 6
2Y2 7
1A3 8
2Y3 9
GND⁽¹⁾
19 2OE
18 1Y0
17 2A0
16 1Y1
15 2A1
14 1Y2
13 2A2
12 1Y3
aaa-003158
Transparent top view
(1) This is not a supply pin. The substrate is attached to this
pad using conductive die attach material. There is no
electrical or mechanical requirement to solder this pad.
However, if it is soldered, the solder land should remain
floating or be connected to GND.
Fig 5. Pin configuration DHVQFN20
5.2 Pin description
Table 2. Pin description
Symbol
Pin
1OE, 2OE
1, 19
1A0, 1A1, 1A2, 1A3
2, 4, 6, 8
2Y0, 2Y1, 2Y2, 2Y3
3, 5, 7, 9
GND
10
2A0, 2A1, 2A2, 2A3
17, 15, 13, 11
1Y0, 1Y1, 1Y2, 1Y3
18, 16, 14, 12
V_CC
20
Description
output enable input (active LOW)
data input
bus output
ground (0 V)
data input
bus output
supply voltage
74HC_HCT240_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 30 July 2012
© NXP B.V. 2012. All rights reserved.
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