74HC00D Datasheet, PDF (3/16 Pages) NXP Semiconductors – Quad 2-input NAND gate

NXP Semiconductors
74HC00; 74HCT00
Quad 2-input NAND gate
Table 2.
Symbol
1Y to 4Y
GND
V_CC
Pin description …continued
Pin
Description
3, 6, 8, 11
data output
7
ground (0 V)
14
supply voltage
6. Functional description
Table 3. Function table^[1]
Input
nA
nB
L
X
X
L
H
H
[1] H = HIGH voltage level; L = LOW voltage level; X = don’t care.
7. Limiting values
Output
nY
H
H
L
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
Parameter
Conditions
Min Max Unit
V_CC
I_IK
I_OK
I_O
I_CC
I_GND
T_stg
P_tot
supply voltage
input clamping current
output clamping current
output current
supply current
ground current
storage temperature
total power dissipation
DIP14 package
V_I < 0.5 V or V_I > V_CC + 0.5 V
V_O < 0.5 V or V_O > V_CC + 0.5 V
0.5 V < V_O < V_CC + 0.5 V
0.5
[1] _-
[1] _-
-
-
50
65
[2]
-
+7
V
20 mA
20 mA
25 mA
50
mA
-
mA
+150 C
750 mW
SO14, (T)SSOP14 and
DHVQFN14 packages
-
500 mW
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] For DIP14 package: P_tot derates linearly with 12 mW/K above 70 C.
For SO14 package: P_tot derates linearly with 8 mW/K above 70 C.
For (T)SSOP14 packages: P_tot derates linearly with 5.5 mW/K above 60 C.
For DHVQFN14 packages: P_tot derates linearly with 4.5 mW/K above 60 C.
74HC_HCT00
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 6 — 14 December 2011
© NXP B.V. 2011. All rights reserved.
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