74ALVC32 Datasheet, PDF (3/13 Pages) Fairchild Semiconductor – Low Voltage Quad 2-Input OR Gate with 3.6V Tolerant Inputs and Outputs

NXP Semiconductors
74ALVC32
Quad 2-input OR gate
5.2 Pin description
Table 2.
Symbol
nA
nB
nY
V_CC
GND
Pin description
Pin
1, 4, 9, 12
2, 5, 10, 13
3, 6, 8, 11
14
7
6. Functional description
Description
data input
data input
data output
supply voltage
ground (0 V)
Table 3. Function table^[1]
Input nA
L
L
H
H
[1] H = HIGH voltage level
L = LOW voltage level
7. Limiting values
Input nB
L
H
L
H
Output nY
L
H
H
H
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
Parameter
Conditions
Min
Max
Unit
V_CC
supply voltage
−0.5 +4.6
V
I_IK
input clamping current
V_I < 0 V
−50
-
mA
V_I
input voltage
−0.5 +4.6
V
I_OK
output clamping current
V_O > V_CC or V_O < 0 V
-
±50
mA
V_O
output voltage
output HIGH or LOW state
[1] [2] _−0.5
V_CC + 0.5 V
output 3-state
−0.5 +4.6
V
I_O
output current
power-down mode, V_CC = 0 V
[2] _−0.5
+4.6
V
V_O = 0 V to V_CC
-
±50
mA
I_CC
I_GND
T_stg
P_tot
supply current
ground current
storage temperature
total power dissipation
T_amb = −40 °C to +85 °C
-
100
mA
−100 -
mA
−65
+150
°C
[3] _-
500
mW
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] When V_CC = 0 V (power-down mode), the output voltage can be 3.6 V in normal operation.
[3] For SO14 packages: above 70 °C derate linearly with 8 mW/K.
For TSSOP14 packages: above 60 °C derate linearly with 5.5 mW/K.
For DHVQFN14 packages: above 60 °C derate linearly with 4.5 mW/K.
74ALVC32_2
Product data sheet
Rev. 02 — 10 December 2007
© NXP B.V. 2007. All rights reserved.
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