PCF85063ATL Datasheet, PDF (29/54 Pages) NXP Semiconductors – Tiny Real-Time Clock/calendar with alarm function and I2C-bus

NXP Semiconductors
PCF85063ATL
Tiny Real-Time Clock/calendar with alarm function and I²C-bus
When the TIE flag is set, an interrupt signal on INT is generated if this mode is enabled.
See Section 8.2.2 for details on how the interrupt can be controlled.
When starting the timer for the first time, the first period has an uncertainty. The
uncertainty is a result of the enable instruction being generated from the interface clock
which is asynchronous from the timer source clock. Subsequent timer periods do not have
such delay. The amount of delay for the first timer period depends on the chosen source
clock, see Table 37.
Table 37. First period delay for timer counter value T
Timer source clock
Minimum timer period
4.096 kHz
T
64 Hz
T
1 Hz
T – 1 + ------¹-------
64 Hz
1_{⁄60 Hz}
T – 1 + ------¹-------
64 Hz
Maximum timer period
T+1
T+1
T + ------¹-------
64 Hz
T + ------¹-------
64 Hz
At the end of every countdown, the timer sets the countdown timer flag (bit TF in register
Control_2). Bit TF can only be cleared by command. The asserted bit TF can be used to
generate an interrupt at pin INT. The interrupt may be generated as a pulsed signal every
countdown period or as a permanently active signal which follows the condition of bit TF.
Bit TI_TP is used to control this mode selection and the interrupt output may be disabled
with bit TIE, see Table 35 and Figure 15.
When reading the timer, the current countdown value is returned and not the initial
value T. Since it is not possible to freeze the countdown timer counter during read back, it
is recommended to read the register twice and check for consistent results.
Timer source clock frequency selection of 1 Hz and ¹â„₆₀ Hz is affected by the Offset
register. The duration of a program period varies according to when the offset is initiated.
For example, if a 100 s timer is set using the 1 Hz clock as source, then some 100 s
periods will contain correction pulses and therefore be longer or shorter depending on the
setting of the Offset register. See Section 8.2.3 to understand the operation of the Offset
register.
8.6.3.1 Countdown timer interrupts
The pulse generator for the countdown timer interrupt uses an internal clock and is
dependent on the selected source clock for the countdown timer and on the countdown
value T. As a consequence, the width of the interrupt pulse varies (see Table 38).
Table 38. INT operation
TF and INT become active simultaneously.
Source clock (Hz)
INT period (s)
T = 1^[1]
4 096
64
1
1_⁄60
1_{⁄8 192}
1_⁄128
1_⁄64
1_⁄64
[1] T = loaded countdown value. Timer stops when T = 0.
T > 1^[1]
1_{⁄4 096}
1_⁄64
1_⁄64
1_⁄64
PCF85063ATL
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 15 April 2013
© NXP B.V. 2013. All rights reserved.
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