P89V660_08 Datasheet, PDF (29/89 Pages) NXP Semiconductors – 8-bit 80C51 5 V low power 16 kB/32 kB/64 kB flash microcontroller with 512 B/1 kB/2 kB RAM, dual I2C-bus, SPI

NXP Semiconductors
P89V660/662/664
80C51 with 512 B/1 kB/2 kB RAM, dual I²C-bus, SPI
The I²C-bus will enter Master Transmitter mode by setting the STA bit. The I²C-bus logic
will send the START condition as soon as the bus is free. After the START condition is
transmitted, the SI bit is set, and the status code in S1STA should be 08H. This status
code must be used to vector to an interrupt service routine where the user should load the
slave address to S1DAT and data direction bit (SLA+W). The SI bit must be cleared before
the data transfer can continue.
When the slave address and R/W bit have been transmitted and an acknowledgment bit
has been received, the SI bit is set again, and the possible status codes are 18H, 20H, or
38H for the master mode or 68H, 78H, or 0B0H if the slave mode was enabled (setting
AA = Logic 1). The appropriate action to be taken for each of these status codes is shown
in Table 22.
S slave address R/W A DATA A DATA A/A P
logic 0 = write
logic 1 = read
data transferred
(n Bytes + acknowledge)
from master to slave
from slave to master
A = acknowledge (SDA LOW)
A = not acknowledge (SDA HIGH)
S = START condition
P = STOP condition
002aaa929
Fig 8. Format in the Master Transmitter mode
6.4.5.2 Master receiver mode
In the Master Receiver mode, data is received from a slave transmitter. The transfer
started in the same manner as in the Master Transmitter mode. When the START
condition has been transmitted, the interrupt service routine must load the slave address
and the data direction bit to I²C-bus Data Register (S1DAT). The SI bit must be cleared
before the data transfer can continue.
When the slave address and data direction bit have been transmitted and an acknowledge
bit has been received, the SI bit is set, and the Status Register will show the status code.
For master mode, the possible status codes are 40H, 48H, or 38H. For slave mode, the
possible status codes are 68H, 78H, or B0H. Refer to Table 24 for details.
S slave address R A DATA A DATA A P
logic 0 = write
logic 1 = read
from master to slave
from slave to master
data transferred
(n Bytes + acknowledge)
A = acknowledge (SDA LOW)
A = not acknowledge (SDA HIGH)
S = START condition
002aaa930
Fig 9. Format of Master Receiver mode
After a repeated START condition, I²C-bus may switch to the Master Transmitter mode.
P89V660_662_664_2
Product data sheet
Rev. 02 — 29 January 2008
© NXP B.V. 2008. All rights reserved.
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