P89V660_08 Datasheet, PDF (28/89 Pages) NXP Semiconductors – 8-bit 80C51 5 V low power 16 kB/32 kB/64 kB flash microcontroller with 512 B/1 kB/2 kB RAM, dual I2C-bus, SPI

NXP Semiconductors
P89V660/662/664
80C51 with 512 B/1 kB/2 kB RAM, dual I²C-bus, SPI
Table 17. I²C-bus clock rates …continued
CR2:0
6-clock mode
Bit frequency at f_osc
12-clock mode
6 MHz
12 MHZ
6 MHz
101
100
200
50
110
200
400
100
111
0.49 < 62.5
0.98 < 50.0
0.24 < 62.5
12 MHz
100
200
0.49 < 62.5
f_osc divided by
6X
60
30
48 x (Timer 1
reload)
12X
120
60
96 x (Timer 1
reload)
6.4.4 I²C-bus status register
This is a read-only register. It contains the status code of the I²C-bus interface. The least
three bits are always 0. There are 26 possible status codes. When the code is F8H, there
is no relevant information available and SI bit is not set. All other 25 status codes
correspond to defined I²C-bus states. When any of these states entered, the SI bit will be
set. Refer to Table 22 to Table 25 for details.
Table 18. I²C-bus status register (S1STA - address D9H) bit allocation
Bit
7
6
5
4
3
2
1
0
Symbol SC.4
SC.3
SC.2
SC.1
SC.0
0
0
0
Reset 0
0
0
0
0
0
0
0
Table 19. I²C-bus status register (S1STA - address D9H) bit description
Bit Symbol Description
7:3 SC[4:0] I²C-bus Status code.
2:0 -
Reserved, are always set to 0.
6.4.5 I²C-bus operation modes
6.4.5.1 Master transmitter mode
In this mode data is transmitted from master to slave. Before the Master Transmitter mode
can be entered, S1CON must be initialized as follows:
Table 20. I²C-bus control register (S1CON - address D8H)
Bit
7
6
5
4
3
2
Symbol CR2
ENS1 STA
STO
SI
AA
Value bit rate 1
0
0
0
x
1
CR1
bit rate
0
CR0
bit rate
CR2:0 define the bit rate (See Table 17). ENS1 must be set to 1 to enable the I²C-bus
function. If the AA bit is 0, it will not acknowledge its own slave address or the general call
address in the event of another device becoming master of the bus and it can not enter
slave mode. STA, STO, and SI bits must be cleared to 0.
The first byte transmitted contains the slave address of the receiving device (7 bits) and
the data direction bit. In this case, the data direction bit (R/W) will be logic 0 indicating a
write. Data is transmitted 8 bits at a time. After each byte is transmitted, an acknowledge
bit is received. START and STOP conditions are output to indicate the beginning and the
end of a serial transfer.
P89V660_662_664_2
Product data sheet
Rev. 02 — 29 January 2008
© NXP B.V. 2008. All rights reserved.
28 of 89