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PCF8534A_08 Datasheet, PDF (27/44 Pages) NXP Semiconductors – Universal LCD driver for low multiplex rates
NXP Semiconductors
PCF8534A
Universal LCD driver for low multiplex rates
11. Static characteristics
Table 16. Static characteristics
VDD = 1.8 V to 5.5 V; VSS = 0 V; VLCD = 2.5 V to 6.5 V; Tamb = −40 °C to +85 °C; unless otherwise specified.
Symbol Parameter
Conditions
Min
Typ Max
Unit
Supplies
VDD
VLCD
IDD
IDD(LCD)
Logic
supply voltage
LCD supply voltage
supply current
LCD supply current
fclk = 1536 Hz
fclk = 1536 Hz
1.8
2.5
[1] -
[1] -
-
5.5
V
-
6.5
V
8
20
µA
24
60
µA
VI
input voltage
VSS − 0.5
VDD + 0.5 V
VIL
LOW-level input voltage
on pins CLK, SYNC, OSC, A0 to A2
VSS
and SA0
-
0.3VDD V
VIH
HIGH-level input voltage
on pins CLK, SYNC, OSC, A0 to A2
0.7VDD
-
VDD
V
and SA0
VPOR
power-on reset voltage
1.0
IOL
LOW-level output current VOL = 0.4 V; VDD = 5 V; on pins CLK
1
and SYNC
1.3 1.6
V
-
-
mA
IOH
HIGH-level output current VOH = 4.6 V; VDD = 5 V; on pin CLK
−1
IL
leakage current
VI = VDD or VSS; on pins SA0, A0 to
−1
A2 and CLK
-
-
mA
-
+1
µA
CI
input capacitance
I2C-bus; pins SDA and SCL
VI = VDD; on pin OSC
−1
[2] -
-
+1
µA
-
7
pF
VI
input voltage
VIL
LOW-level input voltage
VIH
HIGH-level input voltage
IOL
LOW-level output current
IL
leakage current
Ci
input capacitance
LCD outputs
VSS − 0.5 -
pin SCL
VSS
-
pin SDA
VSS
-
0.7VDD
-
VOL = 0.4 V; VDD = 5 V; on pin SDA
3
-
VI = VDD or VSS
−1
-
[2] -
-
5.5
V
0.3VDD V
0.2VDD V
5.5
V
-
mA
+1
µA
7
pF
Output pins BP0, BP1, BP2 and BP3
VBP
voltage on pin BP
RBP
resistance on pin BP
Output pins S0 to S59
Cbpl = 35 nF
VLCD = 5 V
[3] −100
[4] -
-
+100
mV
1.5 10
kΩ
VS
voltage on pin S
RS
resistance on pin S
Csgm = 35 nF
VLCD = 5 V
[5] −100
[4] -
-
+100
mV
6.0 13.5
kΩ
[1] LCD outputs are open circuit; inputs at VSS or VDD; external clock with 50 % duty factor; I2C-bus inactive.
[2] Not tested, design specification only.
[3] Cbpl = backplane capacitance.
[4] Outputs measured individually and sequentially.
[5] Csgm = segment capacitance.
PCF8534A_3
Product data sheet
Rev. 03 — 10 November 2008
© NXP B.V. 2008. All rights reserved.
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