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PCF85133 Datasheet, PDF (27/41 Pages) NXP Semiconductors – Universal LCD driver for low multiplex rates
NXP Semiconductors
PCF85133
Universal LCD driver for low multiplex rates
11. Dynamic characteristics
Table 17. Dynamic characteristics
VDD = 1.8 V to 5.5 V; VSS = 0 V; VLCD = 2.5 V to 6.5 V; Tamb = −40 °C to +85 °C; unless otherwise specified.
Symbol Parameter
Conditions
Min Typ Max
Clock
Internal: output pin CLK
fclk
clock frequency
ffr
frame frequency
External: input pin CLK
FF = VDD
FF = VSS
FF = VDD
FF = VSS
[1][2] 1440
[1][2] 1920
60
80
1970
2640
82
110
2640
3600
110
150
fclk(ext)
external clock frequency
tclk(H)
HIGH-level clock time
tclk(L)
LOW-level clock time
Synchronization: input pin SYNC
[2] 800
-
130 -
130 -
3600
-
-
tPD(SYNC_N) SYNC propagation delay
tSYNC_NL
SYNC LOW time
Outputs: pins BP0 to BP3 and S0 to S79
-
30
-
1
-
-
tPD(drv)
driver propagation delay
I2C-bus: timing[3][4]
VLCD = 5 V
-
-
30
Pin SCL
fSCL
tHIGH
tLOW
Pin SDA
SCL clock frequency
HIGH period of the SCL clock
LOW period of the SCL clock
-
-
400
0.6
-
-
1.3
-
-
tSU;DAT
data set-up time
tHD;DAT
data hold time
Pins SCL and SDA
100 -
-
0
-
-
tBUF
tSU;STO
tHD;STA
tSU;STA
tr
tf
Cb
tw(spike)
bus free time between a STOP and START condition
set-up time for STOP condition
hold time (repeated) START condition
set-up time for a repeated START condition
rise time of both SDA and SCL signals
fall time of both SDA and SCL signals
capacitive load for each bus line
spike pulse width
on bus
1.3
-
-
0.6
-
-
0.6
-
-
0.6
-
-
-
-
0.3
-
-
0.3
-
-
400
-
-
50
Unit
Hz
Hz
Hz
Hz
Hz
µs
µs
ns
µs
µs
kHz
µs
µs
ns
ns
µs
µs
µs
µs
µs
µs
pF
ns
[1] Typical output duty cycle of 50 %.
[2] The corresponding frame frequency is f fr = -f-2--c-4--l-k- .
[3] All timing values are valid within the operating supply voltage and ambient temperature range and are referenced to VIL and VIH with an
input voltage swing of VSS to VDD.
[4] For I2C-bus timings see Figure 19.
PCF85133_1
Product data sheet
Rev. 1 — 17 February 2009
© NXP B.V. 2009. All rights reserved.
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