SC16IS740_11 Datasheet, PDF (26/63 Pages) NXP Semiconductors – Single UART with I2C-bus/SPI interface, 64 bytes of transmit and receive FIFOs

NXP Semiconductors
SC16IS740/750/760
Single UART with I²C-bus/SPI interface, 64-byte FIFOs, IrDA SIR
8.5 Line Status Register (LSR)
Table 16 shows the Line Status Register bit settings.
Table 16. Line Status Register bits description
Bit Symbol Description
7
LSR[7] FIFO data error.
logic 0 = no error (normal default condition)
logic 1 = at least one parity error, framing error, or break indication is in the
receiver FIFO. This bit is cleared when no more errors are present in the
FIFO.
6
LSR[6] THR and TSR empty. This bit is the Transmit Empty indicator.
logic 0 = transmitter hold and shift registers are not empty
logic 1 = transmitter hold and shift registers are empty
5
LSR[5] THR empty. This bit is the Transmit Holding Register Empty indicator.
logic 0 = transmit hold register is not empty
logic 1 = transmit hold register is empty. The host can now load up to
64 characters of data into the THR if the TX FIFO is enabled.
4
LSR[4] break interrupt
logic 0 = no break condition (normal default condition)
logic 1 = a break condition occurred and associated character is 0x00, that
is, RX was LOW for one character time frame
3
LSR[3] framing error
logic 0 = no framing error in data being read from RX FIFO (normal default
condition).
logic 1 = framing error occurred in data being read from RX FIFO, that is,
received data did not have a valid stop bit
2
LSR[2] parity error.
logic 0 = no parity error (normal default condition)
logic 1 = parity error in data being read from RX FIFO
1
LSR[1] overrun error
logic 0 = no overrun error (normal default condition)
logic 1 = overrun error has occurred
0
LSR[0] data in receiver
logic 0 = no data in receive FIFO (normal default condition)
logic 1 = at least one character in the RX FIFO
When the LSR is read, LSR[4:2] reflect the error bits (BI, FE, PE) of the character at the
top of the RX FIFO (next character to be read). Therefore, errors in a character are
identified by reading the LSR and then reading the RHR.
LSR[7] is set when there is an error anywhere in the RX FIFO, and is cleared only when
there are no more errors remaining in the FIFO.
SC16IS740_750_760
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 7 — 9 June 2011
© NXP B.V. 2011. All rights reserved.
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