LH7A404 Datasheet, PDF (26/75 Pages) NXP Semiconductors – 32-Bit System-on-Chip

LH7A404
NXP Semiconductors
32-Bit System-on-Chip
Color LCD Controller
The LH7A404’s LCD Controller is programmable to
support up to 1,024 × 768, 16-bit color LCD panels. It
interfaces directly to STN, color STN, TFT, AD-TFT,
and HR-TFT panels. Unlike other LCD controllers, the
LH7A404’s LCD Controller saves an external timing
ASIC by incorporating the timing conversion logic for
thin LCD modules such as AD-TFT and HR-TFT.
The Color LCD Controller features support for:
• Up to 1,024 × 768 Resolution
• 16-bit Video Bus
• 16 bits-per-pixel (bpp) 5:5:5:1 or 5:6:5 direct color or
on-chip color palette for 1, 2, 4, and 8 bpp resolution
• STN, Color STN, AD-TFT, HR-TFT, TFT panels
– Single and Dual Scan STN panels
– Up to 15 Gray Shades (mono STN)
– Up to 3375 colors (color STN)
– Up to 64 k-Colors
– An on-chip SRAM frame buffer conserves bus
bandwidth and saves active power.
AC97 Codec Controller
The AC97 Codec controller includes a 5-pin serial
interface to an external audio codec. The AC97 link is a
bi-directional, fixed rate, serial Pulse Code Modulated
(PCM) digital stream, dividing each audio frame into 12
outgoing and 12 incoming data streams (slots), each
with 20-bit resolution per sample.
The AC97 controller contains logic that controls the
AC97 link to the audio codec and an interface to the
AMBA APB.
Its main features include:
• Serial-to-parallel conversion for data received from
the external codec
• Parallel-to-serial conversion for data transmitted to
the external codec
• Reception/transmission of control and status infor-
mation via the AMBA APB interface
• Support for up to 4 simultaneous codec sampling
rates with its 4 transmit and 4 receive channels. The
transmit and receive paths are buffered with internal
FIFO memories, allowing data to be stored indepen-
dently in both transmit and receive modes. Three of
the outgoing FIFOs can be written via either the APB
interface or with DMA channels 1-3.
Audio Codec Interface (ACI)
The ACI provides:
• A digital serial interface to an off-chip 8-bit codec
• All the necessary clocks and timing pulses to per-
form serialization or de-serialization of the data
stream to, or from the codec device.
The interface supports full duplex operation and the
transmit and receive paths are buffered with internal
FIFO memories allowing up to 16 bytes to be stored
independently in both transmit and receive modes.
The ACI includes a programmable frequency divider
that generates a common transmit and receive bit clock
output from the on-chip ACI clock input (ACBITCLK).
Transmit data values are output synchronous with the
rising edge of the bit clock output. Receive data values
are sampled on the falling edge of the bit clock output.
The start of a data frame is indicated by a synchroniza-
tion output signal that is coincident with the bit clock.
Pulse Width Modulator (PWM)
The Pulse Width Modulator features:
• Configurable dual output
• Separate input clocks for each PWM output
• 16-bit resolution
• Programmable synchronous mode support allows
external input to start PWM
• Programmable pulse width (duty cycle), interval
(frequency), and polarity
– Static programming: when the PWM is stopped
– Dynamic programming: when the PWM is running
– Updates duty cycle, frequency, and polarity at
end of a PWM cycle
The PWM is a configurable dual-output, dual-clock-
input AMBA slave module, and connects to the APB.
Synchronous Serial Port (SSP)
The SSP is a master-only interface for synchro-
nous serial communication with peripheral devices
that have either Motorola SPI, National Semicon-
ductor MICROWIRE, or Texas Instruments
Synchronous Serial Interfaces.
The SSP performs serial-to-parallel conversion on
data received from a peripheral. The transmit and
receive paths are buffered with internal FIFO memories
allowing up to eight 16-bit values to be stored indepen-
dently in both transmit and receive modes. Serial data
is transmitted on SSPTXD and received on SSPRXD.
The LH7A404 SSP includes a programmable bit rate
clock divider and prescaler to generate the serial output
clock SCLK from the input clock SSPCLK. Bit rates are
supported to 2 MHz and beyond, subject to choice of
frequency for SSPCLK; the maximum bit rate will usu-
ally be determined by peripheral device’s capability.
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Preliminary data sheet