UJA1078 Datasheet, PDF (25/53 Pages) NXP Semiconductors – High-speed CAN/dual LIN core system basis chip

NXP Semiconductors
UJA1078
High-speed CAN/dual LIN core system basis chip
6.8.1 LIN operating modes
6.8.1.1 Active mode
The LIN transceivers will be in Active mode when:
• the SBC is in Normal mode (MC = 10 or 11) and
• the transceivers are enabled (STBCL1 = 0 and/or STBCL2 = 0; see Table 6) and
• the battery voltage (V_BAT) is above the LIN undervoltage recovery threshold, V_uvr(LIN).
In LIN Active mode, the transceivers can transmit and receive data via the LIN bus pins.
The receiver detects data streams on the LIN bus pins (LIN1 and LIN2) and transfers
them to the microcontroller via pins RXDL1 and RXDL2 (see Figure 1) - LIN recessive is
represented by a HIGH level on RXDL1/RXDL2, LIN dominant by a LOW level.
The transmit data streams of the protocol controller at the TXDL inputs (TXDL1 and
TXDL2) are converted by the transmitter into bus signals with optimized slew rate and
wave shaping to minimize EME.
6.8.1.2 Lowpower/Off modes
The LIN transceivers will be in Lowpower mode with bus wake-up detection enabled if bit
STBCLx = 1 (see Table 6). The LIN transceivers can be woken up remotely via pins LIN1
and LIN2 in Lowpower mode.
When the SBC is in Standby mode or Sleep mode (MC = 00 or 01), the LIN transceivers
will be in Off mode if bit STBCLx = 0. The LIN transceivers are powered down completely
in Off mode to minimize quiescent current consumption.
Filters at the receiver inputs prevent unwanted wake-up events due to automotive
transients or EMI.
The wake-up event must remain valid for at least the minimum dominant bus time for
wake-up of the LIN transceivers, t_{wake(busdom)min} (see Table 11).
6.8.2 Fail-safe features
6.8.2.1 General fail-safe features
The following fail-safe features have been implemented:
• Pins TXDL1 and TXDL2 have internal pull-ups towards V_V1 to guarantee safe, defined
states if these pins are left floating
• The current of the transmitter output stage is limited in order to protect the transmitter
against short circuits to pin BAT
• A loss of power (pins BAT and GND) has no impact on the bus lines or on the
microcontroller. There will be no reverse currents from the bus.
6.8.2.2 TXDL dominant time-out function
A TXDL dominant time-out timer circuit prevents the bus lines being driven to a permanent
dominant state (blocking all network communications) if TXDL1 or TXDL2 is forced
permanently LOW by a hardware and/or software application failure. The timer is
UJA1078_2
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 02 — 27 May 2010
© NXP B.V. 2010. All rights reserved.
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