DAC1005D650 Datasheet, PDF (24/41 Pages) NXP Semiconductors – Dual 10-bit DAC, up to 650 Msps; 2´ 4´ and 8´ interpolating

NXP Semiconductors
DAC1005D650
Dual 10-bit DAC, up to 650 Msps; 2× 4× and 8× interpolating
Table 31. Frequencies
Mode
CLK input
(MHz)
Dual-port
160
Dual-port
160
Dual-port
80
Interleaved
320
Interleaved
320
Interleaved
160
Input data rate
(MHz)
160
160
80
320
320
160
Interpolation
2×
4×
8×
2×
4×
8×
Update rate
(Msps)
320
640
640
320
640
640
PLL_DIV[1:0]
01 (/4)
01 (/4)
10 (/8)
00 (/2)
00 (/2)
01 (/4)
The settings applied to PLL_PHASE[1:0] (register 02h[2:1]) and PLL_POL
(register 02h[0]), allows adjustment of the phase and polarity of the sampling clock. This
occurs at the input of the DAC core and depends mainly on the sampling frequency. Some
examples are given in Table 32 “Sample clock phase and polarity examples”.
Table 32. Sample clock phase and polarity examples
Mode
Input data rate Interpolation Update rate
(MHz)
(Msps)
Dual-port
80
2×
160
Dual-port
80
4×
320
Dual-port
80
8×
640
Interleaved
160
2×
160
Interleaved
160
4×
320
Interleaved
160
8×
640
PLL_PHASE PLL_POL
[1:0]
01
1
01
0
01
1
01
1
01
0
01
1
DAC1005D650_1
Product data sheet
Rev. 01 — 28 July 2009
© NXP B.V. 2009. All rights reserved.
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