DAC1005D650 Datasheet, PDF (15/41 Pages) NXP Semiconductors – Dual 10-bit DAC, up to 650 Msps; 2´ 4´ and 8´ interpolating

NXP Semiconductors
DAC1005D650
Dual 10-bit DAC, up to 650 Msps; 2× 4× and 8× interpolating
The SPI timing characteristics are given in Table 8.
Table 8. SPI timing characteristics
Symbol
Parameter
f_SCLK
t_w(SCLK)
t_{su(SCS_N)}
t_{h(SCS_N)}
t_su(SDIO)
t_h(SDIO)
t_{w(RESET_N)}
SCLK frequency
SCLK pulse width
SCS_N set-up time
SCS_N hold time
SDIO set-up time
SDIO hold time
RESET_N pulse width
Min
Typ
-
-
30
-
20
-
20
-
10
-
5
-
30
-
10.2.3 Detailed descriptions of registers
An overview of the details for all registers is provided in Table 9.
Max
Unit
15
MHz
-
ns
-
ns
-
ns
-
ns
-
ns
-
ns
DAC1005D650_1
Product data sheet
Rev. 01 — 28 July 2009
© NXP B.V. 2009. All rights reserved.
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